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研究生： 黃穎俊
Huang, Ying-Jun
論文名稱： 使用BSIM-CMG 進行氧化物半導體建模與SRAM設計以及低溫CMOS SRAM設計
Compact Modeling with BSIM-CMG and SRAM Design for Oxide Semiconductor and Cryogenic CMOS
指導教授： 盧達生
Lu, Dar-Sen
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年： 2024
畢業學年度： 112
語文別： 英文
論文頁數： 83
中文關鍵詞： 氧化物半導體 、緊湊模型 、單體3D 元件 、CMOS SRAM 、低溫 、Vmin 、SNM 、閾值電壓
外文關鍵詞： oxide semiconductors, compact model, M3D, CMOS SRAM, cryogenic, Vmin, SNM, threshold voltage
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    • 本研究著重於開發用於氧化物半導體（如IGZO 和InO）的緊湊模型，並研究其在各種應用中的行為。氧化物半導體因其高遷移率、透明性、低溫加工能力和適用於大面積基板的優點，在現代電子設備中具有重要應用。透過使用BSIM-CMG 模型，我們可以精確模擬這些氧化物半導體薄膜晶體管（TFTs）的特性，並進一步用於基本電路如反相器、振盪器和SRAM 電路，或是其他基於氧化物半導體的Monolithic 3D (M3D)元件的設計和模擬。
    此外，隨著量子計算等前沿技術的發展，CMOS SRAM 在低溫下的特性研究變得愈發重要。低溫操作可以提高SRAM 的電性能，包括增加載流子遷移率、減少漏電流、改善亞閾值擺幅以及臨界電壓的變化，從而提升內存操作的速度和效率。本研究探索了在不同溫度條件(300K, 200K, 120K, 77K, 4K)下的40nm 製程之SRAM 特性，例如最小操作電壓(Vmin) 和靜態噪聲容限（SNM），為低溫環境下的低功耗高效存儲解決方案的開發提供了支持。
    透過結合氧化物半導體建模和低溫CMOS SRAM 測量結果，我們希望推進低溫電子學領域的研究，特別是用於存儲應用的IGZO 基低溫SRAM 的研究。這一整合不僅可以擴展我們在低溫環境下的電子設備理解和能力，還能在未來電子學中實現更可靠的操作和更高的性能。

    This study focuses on developing compact models for oxide semiconductors, such as IGZO and InO, and investigating their behavior in various applications. Oxide semiconductors are of significant importance in modern electronic devices due to their high mobility, transparency, low-temperature processing capability, and suitability for large-area substrates. By employing the BSIM-CMG model, we can accurately simulate the characteristics of these oxide semiconductor thin-film transistors (TFTs) and further use them in the design and simulation of basic circuits such as inverters, oscillators, and SRAM circuits, as well as other oxide semiconductor-based Monolithic 3D (M3D) components.
    In addition, with the advancement of frontier technologies such as quantum computing, the study of CMOS SRAM characteristics at low temperatures has become increasingly important. Low-temperature operation can enhance the electrical performance of SRAM, including increased carrier mobility, reduced leakage current, improved subthreshold slope and changes in threshold voltage, thereby improving the speed and efficiency of memory operations. This study explores the characteristics of 40nm CMOS SRAM under different temperature conditions (300K, 200K, 120K, 77K, 4K), such as the minimum operatingvoltage (Vmin) and static noise margin (SNM), providing support for the development of low-power, high-efficiency memory solutions in cryogenic environments.
    By integrating oxide semiconductor modeling with low-temperature CMOS SRAM measurements, we aim to advance research in the field of cryogenic electronics, particularly the study of IGZO-based cryogenic SRAM for storage applications. This integration not only expands our understanding and capabilities of electronic devices in low-temperature environments but also enables more reliable operation and higher performance in future electronics.

    摘要 I Abstract II Acknowledgement III Content IV List of Figures VI Chapter 1. Introduction 1 1.1 Motivation 1 1.2 Research Objective 4 Chapter 2. Literature Review 5 2.1 Oxide Semiconductor 5 2.1.1 Thin-Film Transistor (TFT) 5 2.1.2 Physics of a-IGZO and InO 6 2.1.2.1 Composition and structure 6 2.1.2.2 Density of States (DOS) 8 2.1.2.3 Fermi-Dirac Distribution and Carrier Density 10 2.1.2.4 Conduction Mechanism 12 2.1.2.5 Field Mobility with Vgs Dependence 13 2.1.2.6 Current and Voltage Relation 15 2.1.2.7 Sub-threshold Region 15 2.1.2.8 Threshold Voltage 16 2.1.2.9 Counterclockwise Hysteresis of Ids-Vgs curve 18 2.1.2.10 Unusual gate current 19 2.2 Cryogenic SRAM 21 2.2.1 Cryogenic physics 21 2.2.1.1 Threshold Voltage 21 2.2.1.2 Surface Roughness and Coulombic Scattering 23 2.2.2 Cryogenic SRAM Characteristics 24 Chapter 3. Methodology 28 3.1 Parameter Extraction 28 3.1.1 BSIM-CMG and Verilog-A 28 3.1.2 Extraction Platform Buildup 29 3.1.3 Parameter Extraction Process 31 3.2 Cryogenic SRAM 34 3.2.1 Design and tape-out 35 3.2.2 Cryogenic SRAM measurement 38 Chapter 4. Results and Discussion 41 4.1 Oxide Semiconductor Compact Modeling 41 4.1.1 Fitting result of InO TFTs 41 4.1.2 Fitting results of a-IGZO TFTs 42 4.2 Oxide Semiconductor Device Circuit Simulation 46 4.2.1 Stacked IGZO Device 46 4.2.2 Inverter simulation 49 4.2.2.1 Inverter for positive threshold voltage 49 4.2.2.2 Inverter for negative threshold voltage 52 4.2.3 Ring Oscillator 54 4.2.4 IGZO SRAM Simulation 56 4.2.4.1 Hold static noise margin of IGZO SRAM 57 4.2.4.2 Read noise margin of SRAM 58 4.3 Cryogenic SRAM characterization 59 4.3.1 Measurement Results 59 4.3.2 Vmin of SRAM 60 4.3.3 SNM of SRAM 62 Chapter 5. Conclusions and Future Work 65 5.1 Conclusions 65 5.1.1 Oxide semiconductor compact modeling and circuit design 65 5.1.2 Cryogenic SRAM characterization 65 5.2 Future works 66 Answers to Thesis Defense Questions 67 Reference 71

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