研究生: |
鄭佳航 Cheng, Chia-Hang |
---|---|
論文名稱: |
於矽穿孔結構上製備氧化鎳電阻式記憶體之研究 The prospective study of nickel oxide-based resistive random-access memory (RRAM) fabricated on the thru-silicon via (TSV) structure. |
指導教授: |
莊文魁
Chuang, Ricky Wen-Kuei |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 微電子工程研究所 Institute of Microelectronics |
論文出版年: | 2017 |
畢業學年度: | 105 |
語文別: | 中文 |
論文頁數: | 96 |
中文關鍵詞: | 電阻式記憶體 、矽穿孔 、三維積體電路 、氧化鎳 |
外文關鍵詞: | Resistive Random Access Memory (RRAM), Through Silicon Via (TSV), Three-dimensional integrated circuits, nickel oxide |
相關次數: | 點閱:162 下載:7 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
矽穿孔(Through Silicon Via, TSV)技術利用垂直鑽孔導通的方式連接晶片,相較於打線(wire bonding)技術大幅縮短導線長度,提供更低的電阻與電感效應,降低功率損耗並增進元件的效能,且擁有異質整合等優點,於應用方面能與各式半導體元件整合。而在記憶體發展趨勢中,電阻式記憶體(Resistive Random Access Memory, RRAM)被視為下個世代的非揮發性記憶體,其相較於快閃記憶體(Flash Memory),擁有結構簡單、較小的面積、操作速度快、低寫入功耗、非揮發性與高操作週期等優點,同時也與CMOS製程相容,在產業界與學術領域中越來越多人投入RRAM的研究中。綜合上述所提及,我們可以預測TSV技術與RRAM元件終將進行整合,故本論文之目的在於將TSV技術與RRAM元件整合並進行探討。
將RRAM整合於TSV之前,首先我們製作四種不同電極結構之氧化鎳RRAM,其中氧化鎳薄膜是利用射頻磁控濺鍍法(Radio Frequency Magnetron Sputtering Method)成長,量測此四種結構RRAM之電流電壓掃描曲線,並探討其穩定性。最後選擇上下電極皆為白金結構的RRAM整合於TSV,並成功量測其電流電壓特性曲線,在耐用度測試上穩定達到100次循環,高低阻態在0.1V時的電流比值達到兩個階數(order),其寫入電壓(set voltage)與拭去電壓(reset voltage)呈現穩定常態分佈,接著在記憶時間(retention time)可靠度方面的量測,其記憶窗口(memory window)在經過10000秒的量測後,依舊保持其優異儲存特性,最後利用曲線擬合(curve fitting)的方式進行內部漏電流機制的探討。
Through Silicon Via (TSV) technology vertically connects the chips arranged in stack, which helps to enhance the chip performance by greatly shortening the length of the conducting wire. On the other side, as the development of memory constantly aiming for faster memory devices with high storage capacity, Resistive Random Access Memory (RRAM) is considered the nonvolatile memory of next generation. It is foreseeable in a near future that the possibility of integrating the TSV platform with RRAM components may one day come to a reality! Therefore, the purpose of this thesis is to evaluate the plausibility of this merger. First, nickel oxide based RRAMs with four different electrode structures were fabricated, of which nickel oxide was grown using a radio frequency magnetron sputtering method. The properties and stability of these four different types of RRAM were evaluated. The platinum was chosen as the top and bottom electrode for RRAM integrated with the TSV structure, and the resultant current-voltage characteristics were duly measured. As for the endurance test, it was stably enough to achieve 100 cycles, and the current contrast ratio between the high and low resistance setting at 0.1V was found to be at least two orders of magnitude. Its set and reset voltage showed a stable normal distribution. Furthermore, the retention time reliability test also demonstrated that the memory window still maintains its excellent storage characteristics after more than 10,000 seconds. Finally, a series of curve fittings was applied to analyze the XPS data set in order to discuss the internal leakage current mechanism.
第一章參考文獻:
[1] Y. Taur et al., "CMOS scaling into the nanometer regime," (in English), Proceedings of the Ieee, vol. 85, no. 4, pp. 486-504, Apr 1997.
[2] M. Wu, Y. I. Alivov, and H. Morkoç, "High-κ dielectrics and advanced channel concepts for Si MOSFET," Journal of Materials Science: Materials in Electronics, vol. 19, no. 10, pp. 915-951, 2008.
[3] R. S. Patti, "Three-dimensional integrated circuits and the future of system-on-chip designs," (in English), Proceedings of the Ieee, vol. 94, no. 6, pp. 1214-1224, Jun 2006.
[4] J. H. Lau, "Evolution, challenge, and outlook of TSV, 3D IC integration and 3d silicon integration," Advanced Packaging Materials, pp. 462-488, 2011.
[5] R. Ghaffarian, "Microelectronics packaging technology roadmaps, assembly reliability, and prognostics," Facta universitatis - series: Electronics and Energetics, vol. 29, no. 4, pp. 543-611, 2016.
[6] J. H. Lau, "Overview and outlook of through‐silicon via (TSV) and 3D integrations," Microelectronics International, vol. 28, no. 2, pp. 8-22, 2011.
[7] M. H. Lankhorst, B. W. Ketelaars, and R. A. Wolters, "Low-cost and nanoscale non-volatile memory concept for future silicon chips," Nat Mater, vol. 4, no. 4, pp. 347-52, Apr 2005.
[8] J. S. Meena, S. M. Sze, U. Chand, and T.-Y. Tseng, "Overview of emerging nonvolatile memory technologies," Nanoscale research letters, vol. 9, no. 1, p. 526, 2014.
[9] H. S. P. Wong et al., "Metal Oxide RRAM," Proceedings of the IEEE, vol. 100, no. 6, pp. 1951-1970, 2012.
[10] R. Micheloni, 3D Flash memories. Springer, 2016.
[11] J. Gubbi, R. Buyya, S. Marusic, and M. Palaniswami, "Internet of Things (IoT): A vision, architectural elements, and future directions," Future Generation Computer Systems, vol. 29, no. 7, pp. 1645-1660, 2013.
[12] A. Steegen, "Technology innovation in an IoT Era," in VLSI Technology (VLSI Technology), 2015 Symposium on, 2015, pp. C170-C171: IEEE.
[13] J. U. Knickerbocker et al., "3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias," IEEE Journal of Solid-State Circuits, vol. 41, no. 8, pp. 1718-1725, 2006.
[14] J.-Q. Lu, "3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems," Proceedings of the IEEE, vol. 97, no. 1, pp. 18-30, 2009.
[15] S. William, "Semiconductive wafer and method of making the same," ed: Google Patents, 1962.
[16] M. G. Smith and S. Emanuel, "Methods of making thru-connections in semiconductor wafers," ed: Google Patents, 1967.
[17] M. Sekiguchi et al., "Novel low cost integration of through chip interconnection and application to CMOS image sensor," in Electronic Components and Technology Conference, 2006. Proceedings. 56th, 2006, p. 8 pp.: IEEE.
[18] M. Motoyoshi and M. Koyanagi, "3D-LSI technology for image sensor," Journal of Instrumentation, vol. 4, no. 03, pp. P03009-P03009, 2009.
[19] K. Kim, "Technology for sub-50nm DRAM and NAND flash manufacturing," in Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, 2005, pp. 323-326: IEEE.
[20] G. H. Loh, "3D-Stacked Memory Architectures for Multi-core Processors," presented at the 2008 International Symposium on Computer Architecture, 2008.
[21] B. Black et al., "Die stacking (3D) microarchitecture," in Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, 2006, pp. 469-479: IEEE Computer Society.
[22] J. Simmons and R. Verderber, "New conduction and reversible memory phenomena in thin insulating films," in Proceedings of the Royal Society of London A: Mathematical, Physical and Engineering Sciences, 1967, vol. 301, no. 1464, pp. 77-102: The Royal Society.
[23] L. Chua, "Memristor-the missing circuit element," IEEE Transactions on circuit theory, vol. 18, no. 5, pp. 507-519, 1971.
[24] D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, "The missing memristor found," nature, vol. 453, no. 7191, pp. 80-83, 2008.
[25] M. G. Kim et al., "Study of transport and dielectric of resistive memory states in NiO thin film," Japanese journal of applied physics, vol. 44, no. 10L, p. L1301, 2005.
[26] Y.-T. Chen et al., "Tristate Operation in Resistive Switching of Thin Films," IEEE electron device letters, vol. 33, no. 12, pp. 1702-1704, 2012.
[27] A. Chen et al., "Non-volatile resistive switching for advanced memory applications," in Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, 2005, pp. 746-749: IEEE.
[28] S. Kim, H. Moon, D. Gupta, S. Yoo, and Y.-K. Choi, "Resistive switching characteristics of sol–gel zinc oxide films for flexible memory applications," IEEE Transactions on Electron Devices, vol. 56, no. 4, pp. 696-699, 2009.
[29] A. Prakash, D. Jana, and S. Maikap, "TaO x-based resistive switching memories: prospective and challenges," Nanoscale research letters, vol. 8, no. 1, p. 418, 2013.
[30] W.-T. Wu, J.-J. Wu, and J.-S. Chen, "Resistive switching behavior and multiple transmittance states in solution-processed tungsten oxide," ACS applied materials & interfaces, vol. 3, no. 7, pp. 2616-2621, 2011.
[31] Y. Wu, B. Lee, and H.-S. P. Wong, "Based RRAM Using Atomic Layer Deposition (ALD) With 1-RESET Current," IEEE electron device letters, vol. 31, no. 12, pp. 1449-1451, 2010.
[32] H. Shima et al., "Voltage polarity dependent low-power and high-speed resistance switching in CoO resistance random access memory with Ta electrode," Applied Physics Letters, vol. 93, no. 11, p. 113504, 2008.
[33] C.-Y. Lin et al., "Effect of Top Electrode Material on Resistive Switching Properties of Film Memory Devices," IEEE Electron Device Letters, vol. 28, no. 5, pp. 366-368, 2007.
[34] S. Yu et al., "Improved uniformity of resistive switching behaviors in HfO2 thin films with embedded Al layers," Electrochemical and Solid-State Letters, vol. 13, no. 2, pp. H36-H38, 2010.
[35] B. Choi et al., "Resistive switching mechanism of TiO 2 thin films grown by atomic-layer deposition," Journal of Applied Physics, vol. 98, no. 3, p. 033715, 2005.
[36] J.-J. Huang, C.-W. Kuo, W.-C. Chang, and T.-H. Hou, "Transition of stable rectification to resistive-switching in Ti/TiO 2/Pt oxide diode," Applied Physics Letters, vol. 96, no. 26, p. 262901, 2010.
[37] S. Rossnagel, A. Sherman, and F. Turner, "Plasma-enhanced atomic layer deposition of Ta and Ti for interconnect diffusion barriers," Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, vol. 18, no. 4, pp. 2016-2020, 2000.
[38] C. Lee, I. Kim, W. Choi, H. Shin, and J. Cho, "Resistive Switching Memory Devices Composed of Binary Transition Metal Oxides Using Sol− Gel Chemistry," Langmuir, vol. 25, no. 8, pp. 4274-4278, 2009.
[39] W.-G. Kim and S.-W. Rhee, "Effect of post annealing on the resistive switching of TiO 2 thin film," Microelectronic Engineering, vol. 86, no. 11, pp. 2153-2156, 2009.
[40] Y. Chen et al., "Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity," in Electron Devices Meeting (IEDM), 2009 IEEE International, 2009, pp. 1-4: IEEE.
[41] J.-J. Huang, Y.-M. Tseng, W.-C. Luo, C.-W. Hsu, and T.-H. Hou, "One selector-one resistor (1S1R) crossbar array for high-density flexible memory applications," in Electron Devices Meeting (IEDM), 2011 IEEE International, 2011, pp. 31.7. 1-31.7. 4: IEEE.
[42] S. H. Chang et al., "Oxide Double‐Layer Nanocrossbar for Ultrahigh‐Density Bipolar Resistive Memory," Advanced materials, vol. 23, no. 35, pp. 4063-4067, 2011.
[43] F. Zhuge et al., "Improvement of resistive switching in Cu/ZnO/Pt sandwiches by weakening therandomicity of the formation/rupture of Cu filaments," Nanotechnology, vol. 22, no. 27, p. 275204, 2011.
[44] C.-Y. Liu and J.-M. Hsu, "Dispersion improvement of unipolar resistive switching Ni/CuxO/Cu device by bipolar operation method," Microelectronic Engineering, vol. 87, no. 12, pp. 2504-2507, 2010.
[45] R. Jiang, Z. Han, and X. Du, "Reliability/Uniformity improvement induced by an ultrathin TiO 2 insertion in Ti/HfO 2/Pt resistive switching memories," Microelectronics Reliability, vol. 63, pp. 37-41, 2016.
[46] M. Trapatseli, A. Khiat, S. Cortese, A. Serb, D. Carta, and T. Prodromakis, "Engineering the switching dynamics of TiOx-based RRAM with Al doping," Journal of Applied Physics, vol. 120, no. 2, p. 025108, 2016.
[47] P. Bousoulas, S. Stathopoulos, D. Tsialoukis, and D. Tsoukalas, "Low-Power and Highly Uniform 3-b Multilevel Switching in Forming Free TiO 2–x-Based RRAM With Embedded Pt Nanocrystals," IEEE Electron Device Letters, vol. 37, no. 7, pp. 874-877, 2016.
第二章參考文獻:
[1] M. Motoyoshi, "Through-Silicon Via (TSV)," Proceedings of the IEEE, vol. 97, no. 1, pp. 43-48, 2009.
[2] J. P. Gambino, S. A. Adderly, and J. U. Knickerbocker, "An overview of through-silicon-via technology and manufacturing challenges," Microelectronic Engineering, vol. 135, pp. 73-106, 2015.
[3] B. Wu, A. Kumar, and S. Pamarthy, "High aspect ratio silicon etch: A review," Journal of Applied Physics, vol. 108, no. 5, 2010.
[4] A. K. Dubey and V. Yadava, "Experimental study of Nd:YAG laser beam machining—An overview," Journal of Materials Processing Technology, vol. 195, no. 1-3, pp. 15-26, 2008.
[5] C. W. Tang, H. T. Young, and K. M. Li, "Innovative through-silicon-via formation approach for wafer-level packaging applications," Journal of Micromechanics and Microengineering, vol. 22, no. 4, 2012.
[6] H. Pantsar et al., "Laser microvia drilling and ablation of silicon using 355 nm pico and nanosecond pulses," in Proc. ICALEO, 2008.
[7] A. Elfadel, M. Ibrahim, and G. Fettweis, "3D stacked chips," ed: Springer, 2016.
[8] N. Ranganathan, D. Y. Lee, L. Youhe, G.-Q. Lo, K. Prasad, and K. L. Pey, "Influence of Bosch etch process on electrical isolation of TSV structures," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 10, pp. 1497-1507, 2011.
[9] A. Kamto, R. Divan, A. V. Sumant, and S. L. Burkett, "Cryogenic inductively coupled plasma etching for fabrication of tapered through-silicon vias," Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films, vol. 28, no. 4, pp. 719-725, 2010.
[10] R. Dussart, T. Tillocher, P. Lefaucheux, and M. Boufnichel, "Plasma cryogenic etching of silicon: from the early days to today's advanced technologies," Journal of Physics D: Applied Physics, vol. 47, no. 12, 2014.
[11] D. Archard, K. Giles, A. Price, S. Burgess, and K. Buchanan, "Low temperature PECVD of dielectric films for TSV applications," in Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th, 2010, pp. 764-768: IEEE.
[12] K. Fujimoto, N. Maeda, H. Kitada, K. Suzuki, T. Nakamura, and T. Ohba, "TSV (through silicon via) interconnection on wafer-on-a-wafer (WOW) with MEMS technology," in Solid-State Sensors, Actuators and Microsystems Conference, 2009. TRANSDUCERS 2009. International, 2009, pp. 1877-1880: IEEE.
[13] T. M. Bauer, S. L. Shinde, J. E. Massad, and D. L. Hetherington, "Front end of line integration of high density, electrically isolated, metallized through silicon vias," in Electronic Components and Technology Conference, 2009. ECTC 2009. 59th, 2009, pp. 1165-1169: IEEE.
[14] A. Pecora, L. Maiolo, G. Fortunato, and C. Caligiore, "A comparative analysis of silicon dioxide films deposited by ECR-PECVD, TEOS-PECVD and Vapox-APCVD," Journal of Non-Crystalline Solids, vol. 352, no. 9-20, pp. 1430-1433, 2006.
[15] H. Horie, M. Imai, A. Itoh, and Y. Arimoto, "Novel high aspect ratio aluminum plug for logic/DRAM LSIs using polysilicon-aluminum substitute (PAS)," in Electron Devices Meeting, 1996. IEDM'96., International, 1996, pp. 946-948: IEEE.
[16] J. H. Lau, "Overview and outlook of through‐silicon via (TSV) and 3D integrations," Microelectronics International, vol. 28, no. 2, pp. 8-22, 2011.
[17] C. S. Selvanayagam, J. H. Lau, X. Zhang, S. Seah, K. Vaidyanathan, and T. Chai, "Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps," IEEE Transactions on Advanced Packaging, vol. 32, no. 4, pp. 720-728, 2009.
[18] H. Chang et al., "TSV process using bottom-up Cu electroplating and its reliability test," in Electronics System-Integration Technology Conference, 2008. ESTC 2008. 2nd, 2008, pp. 645-650: IEEE.
[19] S. C. Chen, T. Y. Kuo, Y. C. Lin, and H. C. Lin, "Preparation and properties of p-type transparent conductive Cu-doped NiO films," Thin Solid Films, vol. 519, no. 15, pp. 4944-4947, 2011.
[20] H.-L. Chen, Y.-M. Lu, J.-Y. Wu, and W.-S. Hwang, "Effects of substrate temperature and oxygen pressure on crystallographic orientations of sputtered nickel oxide films," Materials transactions, vol. 46, no. 11, pp. 2530-2535, 2005.
[21] I. Hotový, D. Buc, Š. Haščík, and O. Nennewitz, "Characterization of NiO thin films deposited by reactive sputtering," Vacuum, vol. 50, no. 1-2, pp. 41-44, 1998.
[22] H. Y. Chou et al., "Electronic structure of NiO layers grown on Al2O3 and SiO2 using metallo-organic chemical vapour deposition," Journal of Applied Physics, vol. 110, no. 11, 2011.
[23] M. Tachiki, T. Hosomi, and T. Kobayashi, "Room-temperature heteroepitaxial growth of NiO thin films using pulsed laser deposition," Japanese Journal of Applied Physics, vol. 39, no. 4R, p. 1817, 2000.
[24] D. Y. Jiang, J. M. Qin, X. Wang, S. Gao, Q. C. Liang, and J. X. Zhao, "Optical properties of NiO thin films fabricated by electron beam evaporation," Vacuum, vol. 86, no. 8, pp. 1083-1086, 2012.
[25] R. C. Korošec and P. Bukovec, "Sol-gel prepared NiO thin films for electrochromic applications," Acta Chim. Slov, vol. 53, no. 53, pp. 136-147, 2006.
[26] S. C. Chen, T. Y. Kuo, and T. H. Sun, "Microstructures, electrical and optical properties of non-stoichiometric p-type nickel oxide films by radio frequency reactive sputtering," Surface and Coatings Technology, vol. 205, pp. S236-S240, 2010.
[27] J.-W. Park, J.-W. Park, K. Jung, M. K. Yang, and J.-K. Lee, "Influence of oxygen content on electrical properties of NiO films grown by rf reactive sputtering for resistive random-access memory applications," Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, vol. 24, no. 5, 2006.
[28] J. S. Meena, S. M. Sze, U. Chand, and T.-Y. Tseng, "Overview of emerging nonvolatile memory technologies," Nanoscale research letters, vol. 9, no. 1, p. 526, 2014.
[29] D. A. Buck, "Ferroelectrics for Digital Information Storage and Switching," MASSACHUSETTS INST OF TECH CAMBRIDGE DIGITAL COMPUTER LAB1952.
[30] 鄭佩慈, "鐵電材料之特性與應用," 儀科中心簡訊68期, 2005.
[31] 李. 葉林秀, 徐明豐,吳德和, "磁阻式隨機存取記憶體技術的發展—現在與未來," 物理雙月刊(廿六券四期), 2004.
[32] K. Kim and S. J. Ahn, "Reliability investigations for manufacturable high density PRAM," in Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International, 2005, pp. 157-162: IEEE.
[33] H.-S. P. Wong et al., "Phase change memory," Proceedings of the IEEE, vol. 98, no. 12, pp. 2201-2227, 2010.
[34] H.-S. P. Wong et al., "Metal–oxide RRAM," Proceedings of the IEEE, vol. 100, no. 6, pp. 1951-1970, 2012.
[35] J. J. Yang, D. B. Strukov, and D. R. Stewart, "Memristive devices for computing," Nature nanotechnology, vol. 8, no. 1, pp. 13-24, 2013.
[36] W. Zhuang et al., "Novel colossal magnetoresistive thin film nonvolatile resistance random access memory (RRAM)," in Electron Devices Meeting, 2002. IEDM'02. International, 2002, pp. 193-196: IEEE.
[37] A. Sawa, "Resistive switching in transition metal oxides," Materials today, vol. 11, no. 6, pp. 28-36, 2008.
[38] Y. Li et al., "Conductance quantization in resistive random access memory," Nanoscale research letters, vol. 10, no. 1, p. 420, 2015.
[39] S. Chang et al., "Effects of heat dissipation on unipolar resistance switching in Pt∕ Ni O∕ Pt capacitors," Applied Physics Letters, vol. 92, no. 18, p. 183507, 2008.
[40] X. Guo, C. Schindler, S. Menzel, and R. Waser, "Understanding the switching-off mechanism in Ag+ migration based resistively switching model systems," Applied Physics Letters, vol. 91, no. 13, p. 133513, 2007.
[41] K. Kamiya et al., "ON-OFF switching mechanism of resistive–random–access–memories based on the formation and disruption of oxygen vacancy conducting channels," Applied Physics Letters, vol. 100, no. 7, p. 073502, 2012.
[42] F. Verbakel, S. C. Meskers, and R. A. Janssen, "Electronic memory effects in diodes of zinc oxide nanoparticles in a matrix of polystyrene or poly (3-hexylthiophene)," Journal of Applied Physics, vol. 102, no. 8, p. 083701, 2007.
[43] E. L. Murphy and R. Good Jr, "Thermionic emission, field emission, and the transition region," Physical review, vol. 102, no. 6, p. 1464, 1956.
[44] J. Frenkel, "On pre-breakdown phenomena in insulators and electronic semi-conductors," Physical Review, vol. 54, no. 8, p. 647, 1938.
[45] J. G. Simmons, "Poole-Frenkel effect and Schottky effect in metal-insulator-metal systems," Physical Review, vol. 155, no. 3, p. 657, 1967.
[46] P. Mark and W. Helfrich, "Space‐charge‐limited currents in organic crystals," Journal of Applied Physics, vol. 33, no. 1, pp. 205-215, 1962.
[47] A. Rose, "Space-charge-limited currents in solids," Physical Review, vol. 97, no. 6, p. 1538, 1955.
[48] R. K. Chanana et al., "Fowler–Nordheim hole tunneling in p-SiC/SiO2 structures," Applied Physics Letters, vol. 77, no. 16, pp. 2560-2562, 2000.
[49] M. Lenzlinger and E. H. Snow, "Fowler‐Nordheim Tunneling into Thermally Grown SiO2," Journal of Applied Physics, vol. 40, no. 1, pp. 278-283, 1969.
[50] D. Ielmini and Y. Zhang, "Analytical model for subthreshold conduction and threshold switching in chalcogenide-based memory devices," Journal of Applied Physics, vol. 102, no. 5, p. 054517, 2007.
第四章參考文獻:
[1] J. Y. Son and Y. H. Shin, "Direct observation of conducting filaments on resistive switching of NiO thin films," Applied Physics Letters, vol. 92, no. 22, 2008.
[2] K. M. Kim, D. S. Jeong, and C. S. Hwang, "Nanofilamentary resistive switching in binary oxide system; a review on the present statusand outlook," Nanotechnology, vol. 22, no. 25, p. 254002, 2011.
[3] S. Seo et al., "Electrode dependence of resistance switching in polycrystalline NiO films," Applied Physics Letters, vol. 87, no. 26, 2005.
[4] H.-S. P. Wong et al., "Metal–oxide RRAM," Proceedings of the IEEE, vol. 100, no. 6, pp. 1951-1970, 2012.
[5] M. Lenzlinger and E. H. Snow, "Fowler‐Nordheim Tunneling into Thermally Grown SiO2," Journal of Applied Physics, vol. 40, no. 1, pp. 278-283, 1969.
[6] T.-J. Chu et al., "Charge quantity influence on resistance switching characteristic during forming process," IEEE Electron Device Letters, vol. 34, no. 4, pp. 502-504, 2013.
[7] G. Ma, X. Tang, Z. Zhong, H. Zhang, and H. Su, "Effect of Ni3+ concentration on the resistive switching behaviors of NiO memory devices," Microelectronic Engineering, vol. 108, pp. 8-10, 2013.
[8] D. Sacchetto, M. Zervas, Y. Temiz, G. De Micheli, and Y. Leblebici, "Resistive Programmable Through-Silicon Vias for Reconfigurable 3-D Fabrics," IEEE Transactions on Nanotechnology, vol. 11, no. 1, pp. 8-11, 2012.