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研究生：	賈證主 Chia, Chung-Chu
論文名稱：	為著現代資訊安全協定具有隨機組態設定與管線排程之多元加密系統 Randomly Configured and Pipeline Scheduled Multi-Cipher Cryptosystem for Modern Secure Protocols
指導教授：	楊中平 Young, Chung-Ping
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 資訊工程學系 Department of Computer Science and Information Engineering
論文出版年：	2012
畢業學年度：	100
語文別：	英文
論文頁數：	97
中文關鍵詞：	資訊安全協定、多元加密、硬體排程、單晶網路
外文關鍵詞：	Secure protocols, Multi-cipher, Hardware scheduling, Network on a Chip
相關次數：	點閱：77 下載：0
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本論文主旨在探討如何建構一種具有同時處理多種加密演算法及其加密組態的多核心系統，它可以在每個通訊階段前進行隨機組態設定及多核心加密系統的工作排程，以有效降低現代資訊安全協定中，單一一種演算法及其加密模式以及單一一把金鑰的使用時間，並且提高整個加密系統的資料產出量。隨機組態設定可以有效隱藏每次通訊之中多核心加密系統的組態，系統根據這個組態，在實際進行通訊之前會進行一次多核心處理器的工作排程設計，以獲得最大產出。這個多元加密系統可以在一個通訊階段使用許多的加密核心，每個加密核心能夠使用不同的私密金鑰來獨立執行一種演算法及其工作模式。加密核心可以是一個加密專用的硬體或者是使用微處理器來實現。除此之外，隨機組態設定的結果可能需要大量的加密核心來達到系統最大產出量。因此，傳統匯流排已經無法提供足夠的頻寬來滿足高產出的需求，再加上處理器海的設計容易受到時脈訊號偏移而不穩定。因此，本論文還建構了一個晶片網路模擬平台來解決多核心系統規模增加時的設計問題，這個平台源自於蜘蛛網拓撲，它的架構具有很好的延展性，根據這個單晶網路拓撲，每個晶片中的節點數量是可以做彈性調整的，若要進行系統擴充，也可以很容易的將數個晶片連接起來，以滿足不同組態所需要的核心數量。因此，在現代資訊安全協定中，本論文所提出的多元加密系統不僅可行而且是值得推廣的。

To shorten the exposure time of a specific cipher algorithm as a communication session has been sustained for long, the employment of automatic switch between multiple cipher algorithms per session basis is proposed. In addition, to hide the scheduling sequence and upgrade the throughput, random configuration and pipelined scheduling for diverse encryption bursts are proposed. Furthermore, when the proposed cryptosystem requires a large number of cipher cores, a simplified and extensible spidegon network-on-chip (NoC) platform is built and simulated to provide enough bandwidth and resolve clock skew problems for sea-of-processor implementations.
It is obvious that merely employing a single cipher algorithm with a specific mode of operation and a single session key per session basis in nowadays secure protocols may ease a continuous tracking of a specific cipher algorithm over a communication session. Therefore, a piece of broken information leads to the decipherment of whole session information. Due to frequent switch between diverse cipher suits in the proposed cryptosystem, each encryption burst is short and independent. Even if a short burst is broken, the impact to the whole session information may be still negligible. Consequently, the proposed cryptosystem is worthy to be promoted for modern secure protocols.

Content
Content  IV
List of Tables    	VII

List of Figures	VIII

1   Introduction	1
    1.1   Classification of Cryptosystems．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	1
    1.2   Modern Secure Protocols．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	3
1.3   FPGAs vs. ASICs in Cipher Hardware Implementations．．．．．．．．．．．．	7
1.4   The Shortcomings in Modern Secure Protocols．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	9
1.5   Sea-of-Processor Cryptosystem via NoCs．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	9
1.6   Features of the Proposed Cryptosystem．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	10
2   Literature Review	13
2.1   Single Cipher per Session Basis．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	13
2.2   Multiple Ciphers per Session Basis．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	15
2.3   Dedicated vs. MCU-Based Hardware Accelerators．．．．．．．．．．．．．．．．．．．．．．．．．	16
3   Fast Multi-Cipher Transformation	18
3.1   Cipher Bursts Scheduling．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	18
3.1.1   General form．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	20
3.1.2   Special form in uniform length allocation．．．．．．．．．．．．．．．．．．．．．．．．．．	22
3.2   Fast Multi-Cipher Transformation．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	24
3.2.1   Reversible and pipelined model ．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	24
      3.2.2   Scheduling algorithm．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	26
3.2.3   Throughput estimation．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	28
3.3   Design of a Sample FMCT Accelerator．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	30
      3.3.1  The underlined hardware using a sample FMCT．．．．．．．．．．．．．．．．．	30
3.3.2  Base cipher cores．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	31
3.3.3  Control registers access and data dispatching via PLB-IPIF．．	35
3.3.4  Performance evaluation．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	37
4   Random Configuration and Pipeline Scheduling for MCU-based Multi-cipher Cryptosystem	
40
4.1   Random Configuration．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	40
4.2   Pipeline Scheduling after Random Configuration．．．．．．．．．．．．．．．．．．．．．．．．．．	43
4.3   Example of a Random Configuration and Its Scheduling．．．．．．．．．．．．．．．．．	45
4.4   Critical Exposure Time．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	47
5   Simulation Platform and Simulation Result	49
5.1   An Extensible Spidergon NoC．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	49
5.1.1  Design overview．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	49
5.1.2  Modilfied Wishbone bus．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	51
5.1.3  Basic components．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	54
5.2   IP Address and MASK Assignment．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	57
5.3   Deadlock Prevention．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	59
5.3.1  The retrying mechanism．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	59
5.3.2  Deadlock conditions．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	61
5.3.3  Deadlock prevention with virtual output queue．．．．．．．．．．．．．．．．．．．	63
5.3.4  Simulation of deadlock prevention．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	65
5.4   Packet Latency Analysis．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	70
5.4.1  Local packet latency analysis．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	70
5.4.2  Global packet latency analysis．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	72
5.5   A Simplified Spidergon NoC for the Proposed Cryptosystem．．．．．．．．．．．．	75
5.5.1  Virtual encryption burst．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	77
5.5.2  Scheduled packet latency and throughput estimation．．．．．．．．．．	78
5.6   Simulation of an 16-node NoC multi-cipher cryptosystem．．．．．．．．．．．．	81
5.6.1  Pipeline scheduling using uniform length allocation and virtual encryption time．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	
81
5.6.2  Packet switching overhead．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	84
5.7   Recommended topology．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	87
6   Conclusion．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	89
Bibliography．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	91
Biographical notes．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	97

 
List of Tables
Table 2.1  Related hardware accelerators for modern secure protocols.．．．．．．．．．．．．．	15
Table 3.1  Performance of cipher implementations using FPGA.．．．．．．．．．．．．．．．．．．．．．．．．．	38
Table 3.2  Resource consumption of Vertex-II Pro XPC2VP30 FF896-7．．．．．．．．．．．	38
Table 4.1  Example of diverse cipher suits to clarify the cipher bursts scheduling	45
Table 4.2  Example of diverse cipher bursts scheduling based on Table 3.3. ．．．．．．．	46

 
List of Figures
Figure 1.1   Secure socket layer protocol．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	3
Figure 1.2   Overview of the SSL handshake．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	5
Figure 1.3   An on-chip-network cryptosystem．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	11
Figure 3.1   The encrypting burst of EEj．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	19
Figure 3.2   Timing diagram of randomly scheduled encrypting elements with diverse encrypting burst．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	
20
Figure 3.3   Timing diagram of pipeline scheduled encrypting elements with diverse encrypting burst．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	
21
Figure 3.4   The encryption burst of EEj．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	23
Figure 3.5   Pipelined model of crypto-coprocessors for encrypting．．．．．．．．．．．．．．．	25
Figure 3.6   Pipeline model of crypto-coprocessors for decrypting．．．．．．．．．．．．．．．	25
Figure 3.7   The scheduling algorithm for system configuration．．．．．．．．．．．．．．．．．．	27
Figure 3.8   Hardware block diagram．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	31
Figure 3.9   PLB IPIF Block Diagram．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	36
Figure 3.10  A tested data set for sample FMCT．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	39
Figure 4.1   A MCU-based encryption element with a network interface．．．．．．．．．．	41
Figure 4.2   Diverse cipher bursts scheduling for maximizing the throughput．．．．．．	42
Figure 5.1   Commonly used NoC topologies．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	50
Figure 5.2   An extensible spidergon NoC with size=4 in each granularity．．．．．．．．	51
Figure 5.3   A NI with wishbone bus．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	52
Figure 5.4   A TX controller．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	53
Figure 5.5   A RX controller．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	53
Figure 5.6   Domain chart．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	58
Figure 5.7   IP and MASK assigned in each layer．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	58
Figure 5.8   Example of IP and MASK assignment．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	59
Figure 5.9   A deadlock condition occurs between two nodes．．．．．．．．．．．．．．．．．．．．	61
Figure 5.10  Deadlock condition occurs in circulant transmission．．．．．．．．．．．．．．．．．．．．	62
Figure 5.11  A virtual output queue before a TX interface．．．．．．．．．．．．．．．．．．．．	62
Figure 5.12  A state machine for packet switching via a VOQ．．．．．．．．．．．．．．．．．．．．	64
Figure 5.13  Simulation for deadlock condition between two nodes．．．．．．．．．．．．．．．．．．．．	64
Figure 5.14  Simulation for deadlock condition between two nodes．．．．．．．．．．．．．．．．．．．．	67
Figure 5.15  Simulation for deadlock prevention between couple nodes．．．．．．．．．．	67
Figure 5.16  Parameters set for a deadlock condition in circulant transmission mode．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	
68
Figure 5.17  Simulation for deadlock condition in a circulant transmission mode	65
Figure 5.18  Simulation for deadlock prevention in a circulant transmission mode via VOQs．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	69
Figure 5.19  Maximum local transport latency．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	70
Figure 5.20  Maximum local packet latency analysis with maximum buffer length=512．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	
74
Figure 5.21  Maximum global packet latency analysis with maximum buffer length=512．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	
74
Figure 5.22  A simplified and extensible spidergon NoC．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	75
Figure 5.23  Packetized plaintext and ciphertext．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	76
Figure 5.24  Scheduled packet latency analysis using virtual encryption time with maximum buffer length=512．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	
79
Figure 5.25  Performance loss due to output delay measured in varied throughput coefficients．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	
79
Figure 5.26  an 16-node NoC multi-cipher cryptosystem for simulation．．．．．．．．．．．．．．．	82
Figure 5.27  A pipeline scheduled multi-cipher cryptosystem with 14 encryption elements．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	
82
Figure 5.28  Timing diagram of a pipeline scheduled multi-cipher cryptosystem with 14 encryption elements via uniform length allocation．．．．．．．．．．．	
83
Figure 5.29  Simulation result of a multi-cipher cryptosystem shown in figure 5.28 using virtual encryption bursts．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	
83
Figure 5.30  The packet switching overhead (PSO) shown in the simulation result．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	
85
Figure 5.31  Performance loss measured in varied minimum buffer lengths due to packet switch overheads．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	
86
Figure 5.32  A super5-rooted 4-ary complete tree．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	87
Figure 5.33  The proposed OCNC interconnection．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．	88


                                    

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