| 研究生: |
洪偉程 Hung, Wei-Cheng |
|---|---|
| 論文名稱: |
以0.07mm2實現之十二位元每秒二十億次取樣電流式數位類比轉換器 A 12-bit 2GS/s Current-Steering DAC in 0.07mm2 |
| 指導教授: |
郭泰豪
Kuo, Tai-Haur |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering |
| 論文出版年: | 2013 |
| 畢業學年度: | 101 |
| 語文別: | 英文 |
| 論文頁數: | 98 |
| 中文關鍵詞: | 雙模組動態元件匹配 、數位歸零技術 、輸出阻抗補償 、電流源式 、數位類比轉換器 |
| 外文關鍵詞: | dual-mode DEM, digital return-to-zero, output impedance compensation, current-steering, DAC |
| 相關次數: | 點閱:112 下載:12 |
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本論文提出一個十二位元每秒二十億次取樣之電流源式數位類比轉換器設計,解決三個主要的非線性度來源,分別是電流源不匹配、輸出轉換非線性度及有限輸出阻抗,並達到高速高解析的特性。首先,對於電流源不匹配,隨機旋轉式二元權重選取和資料權重平均化這兩種不同的動態元件匹配演算法被採用來針對不同的應用降低不匹配誤差造成的諧波失真。其次,對電流單元採取減少電流開關及非疊接的調整來提升輸出轉換速度並降低轉換非線性度的影響。除此之外,採用重置式的數位歸零技術以進一步增加輸出轉換線性度。最後,對於有限輸出阻抗的問題,提出一個輸出阻抗補償電路來補償電流單元的非線性阻抗曲線。透過解決這些非線性度的來源,此數位類比轉換器在高取樣速率下仍表現優異。
此電流源式數位類比轉換器之實現是採用TSMC 90奈米,1P9M互補金氧半導體製程,主動電路面積僅0.07平方毫米。量測結果顯示,此數位類比轉換器可達到在十億赫茲取樣頻率下從低頻到四億赫茲的SFDR均大於70dB,且效能指數和世界頂尖的作品相比均為最佳。
In this thesis, a 12-bit 2GS/s current-steering DAC design is presented to overcome the three main nonlinearity sources, which are current source mismatch, output transition nonlinearity, and finite output impedance, and achieve high-speed high-resolution characteristic. Firstly, for the current source mismatch, two different dynamic element matching (DEM) algorithms, random rotation-based binary-weighted selection (RRBS) and data weighted averaging (DWA), are adopted to process the harmonic distortion tones caused by mismatch error for different applications. Secondly, reduced-switch and non-cascoded modifications of the current cells increase the output transition speed and decrease the influence of transition nonlinearity. In addition, a digital resetting return-to-zero (RTZ) is adopted to further enhance the output transition linearity. Finally, for the finite output impedance, an output impedance compensation circuit is proposed to compensate the nonlinear impedance curve of current cells. By dealing with these nonlinearity sources, this DAC performs excellent at high sampling rate.
The current-steering DAC is fabricated in TSMC 90nm 1P9M CMOS technology with only 0.07mm2 of active area. The measurement results show that the DAC achieves >70dB SFDR from dc to 400MHz sampling at 1GHz and performs best in figure of merit (FOM) comparing to state-of-the-art works.
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