在本論文中，探討了三種不同濃度的製程，其輕汲極高壓(HV)金氧半場效電晶體(MOSFET)元件之特性，包含了其基板電流的差異以及克爾克效應(Kirk effect)，與受熱載子影響產生的退化之議題。
首先，對於高壓金氧半場效電晶體元件在市場中的應用與其優點特色做說明。接著描述研究之動機，對於不同輕汲極濃度摻雜之高壓金氧半電晶體，基板電流改變之現象，其延伸之研究。本論文中亦會介紹輕汲極摻雜技術、熱載子效應與元件可靠度之關係、以及分析元件特性之電腦輔助設計(TCAD)模擬軟體。
基礎簡介後，呈現本研究中使用不同輕汲極摻雜濃度製程差異，並且陳述元件的結構與量測的設定與方法，其中包括:元件電流ID-VD 、線性區電流ID-VG、基板電流Isub-VG之量測。
本研究的內容，主要觀察到在不同輕汲極摻雜濃度下，其電流特性的差異，相較於低摻雜濃度下，高摻雜濃度有著更好的基本電流特性，且輕汲極摻雜濃度越低，其基板電流Isub的持續增加現象更為嚴重，因此使用電腦輔助設計(TCAD)模擬軟體來分析員見其衝極化離子效應(Impact Ionization)之分佈以及電場分不，發現其Kirk effect更為嚴重；另一個重點為探討不同輕摻雜濃度在熱載子可靠度方面之差異。文中先敘述了熱載子可靠度量測實驗的設置，並且佐以電腦輔助設計模擬之結果，且我們會確認是否在Isub峰值時其熱載子可靠度是否為最嚴重的地方，最後發現摻雜濃度太輕對可靠度有著相當大的影響，對於未來輕摻雜高壓金氧半場效電晶體的研究有更多的參考。

In the thesis, three process of lightly Doped Drain manufactured high voltage metal-oxide-semiconductor field effect transistors (HV MOSFET) was studied. Devices’ difference of substrate current, kirk effect and hot-carrier-induced degradation was investigated.
First, the advantages and usage of HVMOSFET were illustrated. The motivation of further studying high-voltage device with different LDD doping was presented .Due to the fact that the changing of substrate current. Thus, the devices’ LDD technology , relationship between hot carrier effect and device reliability were performed in the thesis. Also, technology computer aid design(TCAD) was utilized to discuss the details of the devices.
Therefore, the differential between high-voltage devices with different LDD doping were presented in the second part of the thesis, and the structure of the devices and the measurement methodology and setup were also described. Including device current ID-VD, linear region current ID-VG, substrate current Isub-VG .
The main part of the thesis focuses in difference of current characteristic with different LDD doping. The observation of improvement of current characteristic in devices with higher LDD doping. And also indicated that the increasing of substrate current get worse in devices with lower LDD doping. TCAD was used to analysis the mechanism between devices, that is, electric field contour, impact ionization rate contour. The reliability issue was discussed in the thesis, which the hot carrier stress was applied to study the degradation of the devices. TCAD simulation software was used to study the mechanism of the measurement data. And we consume that whether the Isub peak is the worst case of hot carrier stress. At the end, we found that the lower LDD doping is important for reliability.

第一章
[1] Shi, Y., N. Feilchenfeld, R. Phelps, M. Levy, M. Knaipp, and R. Minixhofer (2011), “Drift Design Impact on Quasi-Saturation & HCI for Scalable N-LDMOS”, IEEE International Symposium on Power Semiconductor Devices & IC's, San Diego, May, pp.215~218
[2] Klein, N., S. Levin, G. Fleishon, S. Levy, A. Eyal, and S. Shapira (2008), “Device design tradeoffs for 55v LDMOS driver embedded in 0.18 micronplatform”, IEEE 25th Convention of Electrical and Electronics Engineers in Israel, 2008. IEEEI 2008., Eilat, December, pp. 736~740
[3] B. S. Doyle, Member, IEEE, and K. R. Mistry, Member, IEEE "Anomalous Hot-Carrier Behavior for LDD p-Channel Transistors " IEEE Electron Device Letters VOL.14 No.11 November, 1993
[4] Zitouni, M., F. Morancho, H. Tranduc, P. Rossel, J. Buxo, I. PageÁs, and S. Merchant (1999), “A new lateral power MOSFET for smart power ICs: the ``LUDMOS concept'”, Microelectronics Journal , 30(6), pp. 551~561
[5] Li, Y. Q., C. A. T. Salama, M. Seufert, P. Schvan, and Mike King (1997), “Design and Characterization of Submicron BiCMOS Compatible High-Voltage NMOS and PMOS Devices,” IEEE Transactions on Electron Devices, 44(2), pp. 331~338
[6] Ogura, S., P. J. Tsang, W.W. Walker, D.L. Critchlow, and J.F. Shepard (1981), “Elimination of hot electron gate current by the lightly doped drain-source structure,” IEEE Electron Devices Meeting, International, 27, pp. 651~654
[7] Jone F. CHEN, Kuo-Ming WU, J. R. LEE, Yan-Kuin SU, H. C. WANG, Y. C. LIN , and S. L. HSU "Characteristics and Improvement in Hot-Carrier Reliability of Sub-Micrometer High-Voltage Double Diffused Drain Metal–Oxide–Semiconductor Field-Effect Transistors" Japanese Journal of Applied Physics Vol. 46, No. 4B, 2007, pp. 2019–2022
[8] Jone F. Chen, Tzu-Hsiang Chen and Deng-Ren Ai “Two-stage hot-carrier-induced degradation of p-type LDMOS transistors” IEEE Electronics Letters 6th November 2014 Vol. 50 No. 23 pp. 1751–1753
[9] Jone F. Chen, Member, IEEE, Kuen-Shiuan Tian, Shiang-Yu Chen, Kuo-Ming Wu, J. R. Shih, and Kenneth Wu "Mechanisms of Hot-Carrier-Induced Threshold-Voltage Shift in High-Voltage p-Type LDMOS Transistors" IEEE Transactions on Electron Devices, VOL. 56, NO. 12, DECEMBER 2009
[10] Jone F. Chen, Member, IEEE, Kuen-Shiuan Tian, Shiang-Yu Chen, Kuo-Ming Wu, J. R. Shih, and Kenneth Wu "An Investigation on Anomalous Hot-Carrier-Induced On-Resistance Reduction in n-Type LDMOS Transistors" IEEE Transactions on Device and Materials Reliability, VOL. 9, NO. 3, SEPTEMBER 2009
[11] Hodges, S. ; Microsoft Res. Cambridge, Cambridge, UK, "Prototyping Connected Devices for the Internet of Things" Computer ,Volume:46 , Issue: 2, P.26-P.34
[12] Zanella, A. ; Dept. of Inf. Eng., Univ. of Padova, Padua, Italy "Internet of Things for Smart Cities" ,Internet of Things Journal, IEEE, Vol.1, Issue 1 P.22 - P.32
[13] C. Hu,”Hot-Carrier Effects” in Advanced MOS Device Physics, N. G. Einspruch and G. Gildenblat, Eds Vol.18, VLSI Electronics Microstructure Science, Academic Press, New York, 1989
[14] T.Y. Chan, P.K. Ko, and C. Hu, “A Simple Method to Characterize Substrate Current in MOSFET’s,” IEEE Electron Device Letts EDL-
December 1984
[15] Jun Wang, Rui Li, Yemin Dong, Xin Zou, Li Shao, W.T. Shiau, ”Substrate current characterization and optimization of high voltage LDMOS transistors” Solid-State Electronics January 2008.
[16] Hu, C. M., C. T. Simon, H. Fu-Chieh, P. K. ko, T. Y. Chan, and K. W. Terrill (1985), “Hot-Electron-Induced MOSFET Degradation-Model, Monitor, and Improvement“, IEEE Journal of Solid-State Circuits, 20, pp. 295~305
[17] Wong, Stephen A. Parke, James E . Moon, Hsing-jen C. Wann ,Ping K. KO, and Chenming Hu, “Design for Suppression of Gate-Induced Drain Leakage in LDD MOSFET’s Using a Quasi-Two-Dimensional Analytical Model “lEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 39, NO. 7, JULY 1992, pp.1694~1703
[18] T.Y. Chan', J. Chen, P.K. KO and C. Hu“The Impact of Gate-Induced Drain Leakage Current on MOSFET Scaling “Electron Devices Meeting,VOL. 33,1987, pp 718-721
[19] A. W. Ludikhuize, “Kirk effect limitations in high voltage IC’s” IEEE June 1994.
[20] J.HUI, “A New Substrate and Gate Current Phenomenon in Short-Channel LDD and Minimum Overlap Devices” IEEE Electron Devices Lett Vol. EDL-6 No.3 March 1985
[21] Tech. Dig., Dec. 1982, pp. 718-721.Y. Matsumoto, T. Higuchi, S. Sawada, S. Shinozaki. and 0. Ozawa,“Optimized and reliable LDD structure for 1 pm NMOSFET based on substrate current analysis,” in IEDM Tech. Dig., 1983, pp. 392-395
[22] Silvaco “TCAD World Leader” Silvaco engineered excellence.
第二章
[1] Mikoshiba, H., T Horiuchi, and K. Hamano (1986), “Comparison of Drai Structures in n-Channel MOSFET’s,” IEEE Transactions on Electron Devices, vol.ED-33, no. 1, 1986, pp.140~144
[2] Marius K. Orlowski, Christoph Werner, Joachim P. Klink “Model for the Electric Fields in LDD MOSFET’s Part I: Field Peaks on the Source Side”IEEE Electron Devices Vol. 36. NO. 2 February 1989.
[3] R.Versari,” Hot-Carrier Reliability in Submicrometer LDMOS Transistors”IEEE Electron Devices Lett December 1997
[4] Zitouni, M., F. Morancho, H. Tranduc, P. Rossel, J. Buxo, I. PageÁs, and S. Merchant (1999), “A new lateral power MOSFET for smart power ICs: the LUDMOS concept”, Microelectronics Journal , 30(6), pp. 551~561
[5] Shi, Y., N. Feilchenfeld, R. Phelps, M. Levy, M. Knaipp, and R. Minixhofer (2011), “Drift Design Impact on Quasi-Saturation & HCI for Scalable N-LDMOS”, IEEE International Symposium on Power Semiconductor Devices & IC's, San Diego, May, pp.215~218
[6] Jone F. Chen, Member, IEEE, Kuen-Shiuan Tian, Shiang-Yu Chen, Kuo-Ming Wu, J. R. Shih, and Kenneth Wu "Mechanisms of Hot-Carrier-Induced Threshold-Voltage Shift in High-Voltage p-Type LDMOS Transistors" IEEE Transactions on Electron Devices, VOL. 56, NO. 12, DECEMBER 2009
[7] E.A. Gutierrez, “Second Substrate Current Peak and its Relationship to Gate-Voltage Dependent series resistance in Submicrometer nMOS LDD Transistors.” IEEE Electronics Letters Vol. 28. No. 1 January 1992
[8] Jone F. Chen, Tzu-Hsiang Chen and Deng-Ren Ai “Two-stage hot-carrier-induced degradation of p-type LDMOS transistors” IEEE Electronics Letters 6th November 2014 Vol. 50 No. 23 pp. 1751–1753
[9] Kamata T et al. Jpn J Appl Phys 1976;15(6):1127–33.
[10] Everett E. King, Ronald C. Lacoe and Janet Wang-Ratkovic "The Role of the Spacer Oxide in Determining Worst-case Hot-Carrier Stress Conditions for NMOS LDD Devices "IEEE 00CH37059 38"Annual International Reliability Physics Symposium, San Jose, California, 2000
[11] M.M. Lunenborg, H.C. de Graaff, A.J. Mouthaan, J.F. Verweij "Anomalous NMOSFET Substrate Current Behavior at Accelerated Hot-Carrier Stress Conditions" Solid State Device Research Conference, 1995. ESSDERC '95. Proceedings of the 25th European
[12] T.Y.Huang, ”Stress-Induced Double-Hump Substrate Current in MOSFET’s, ” IEEE Electron Devices Lett Vol. EDL-No.12
[13] E.A. Gutierrez, “Second Substrate Current Peak and its Relationship to Gate-Voltage Dependent series resistance in Submicrometer nMOS LDD Transistors.” IEEE Electronics Letters Vol. 28. No. 1 January 1992
第三章
[1] Landgraf E, Hofmann F, Schulz T, et al. Substrate current and degradation of trench LDD transistors . Solid State Electorn,2002 ,46;965
[2] E.A. Gutierrez, “Second Substrate Current Peak and its Relationship to Gate-Voltage Dependent series resistance in Submicrometer nMOS LDD Transistors.” IEEE Electronics Letters Vol. 28. No. 1 January 1992
[3] F. C. Hsu and K. Y. Chiu, “Evaluation of LDD MOSFET’s based on hot-electron-induced degradation,” iEEE Electron Device Lett., vol. EDL-5, pp. 162-165, May 1984.
第四章
[1] E. Takeda and N. Suzuki, IEEE Electron Device Lett. 4, 111 (1983)
[2] C. Hu, S. C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, and K. W. Terrill, IEEE Trans. Electron Devices 32, 375 (1985)
[3] T. Y. Chan, C. L. Chiang, and H. Gaw, IEEE Trans. Electron Devices 26, 196 (1988)
[4] A. Tanaka, Y. Oritsuki, H. Kikuchihara, M. Miyake, H. J. Mattausch, M. Miura-Mattausch, Y. Lu, and K. Green, IEEE Trans. Electron Devices 58, 2072 (2011).