中文摘要

論文題目：覆晶封裝底部封膠流場之模擬分析
論文題目：Analysis of the Filling Flow of Underfill Encapsulation in Flip Chip Package
研究生：彭星維
指導教授：楊文彬

隨著科技不斷的進步，近年來覆晶封裝朝著縮小化的目標前進，因此造成較小的間距和較密的連接點，首先遇到的問題就是晶片與基板之間的熱膨脹係數差異，錫鉛隆點比以往更容易受到熱應力變化而損毀，因此採用底部封膠的方式由毛細作用吸入膠體於晶片與基板之間，緩和晶片與錫鉛隆點熱膨脹係數的差異與增加可靠度，降低熱應力作用下所造成的疲勞損壞，但由於利用毛細作用充填，充填時間較長，且充填過程中易造成裂縫與封包，因此如何改善充填品質、縮短充填時間與提高生產效能，為覆晶封裝技術發展的主要關鍵。
本研究將底部封膠模擬結果與實驗作對照與修正，採取改變覆晶試片的錫鉛隆點佈植方式，藉此觀察在不同錫鉛隆點佈值方式下，哪種方式對於改善邊際效應所造成的封包現象有較佳的效果，並將搭配點膠間隔時間理想化程式，找出最佳點膠間隔時間，藉以改善積膠與繞膠的現象。

關鍵字：覆晶封裝、底部封膠、封包現象、邊際效應、錫鉛隆點佈植方式

Abstract

Along with advance in technology, Flip Chip has the tendence toward lower profile, lighter weight, and higher density. Due to the mismatch of the coefficients of thermal expansion (CTE) between the chip and substrate, the solder joints tend to fail under high thermal stresses. In order to enhance the reliability of the solder joints, underfill encapsulation is filled into the gap between the chip and substrate around the solder joints by capillary force. The underfill encapsulant is used to decrease the CTE mismatch between chip and substrate. However, the underfill flow is very slow and could be incomplete, leading to the generation of voids. Therefore, it is crucial for flip-chip technology to speed up the encapsulation process and avoid the formation of voids at the same time. In this study, we will compare the result of underfill experiments with the simulations, The behaviors of filling in different bump design model be studied. A systematic method is also proposed to construct the underfill schedule.

Key word : Flip Chip Encapsulation，Underfill，Capillary，Edge Effect，Bump Pitch

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