本論文選擇有蝕刻阻擋層(ESL)的inverted staggered TFT結構，並以a-IGZO為主動層材料，以此構造為基礎，進一步開發雙閘極薄膜電晶體的精簡模型；論文中將以漸進方式來逐步完成模型建立。首先透過相關期刊、論文和書籍研讀TFT元件的歷史和結構，以及了解其通道層材料的演變，並著重於a-IGZO的特性、物理機制與優缺點的討論；之後從研讀的資料中，選擇合適的理論，透過Verilog-A建立出單閘極TFT精簡模型(compact model)，並使用HSPICE呼叫Verilog-A模型進行模擬，利用IGZO TFTs實際測量的數據與模擬結果反覆比較並修正所建立出的精簡模型。
由於本論文的目的為建立雙閘極TFT (DG TFT)的精簡模型，完成單閘極a-IGZO TFT模型的基本電性修正後，進一步在結構上加入第二個閘極(Back Gate, BG)，BG的作用為調整臨界電壓，使TFT在組成電路時與應用上能有更大的調整空間；在此將以DG FD SOI MOSFET相關論文為基礎，討論BG對TFT電性的影響，並在模型中考慮BG的加入，透過模擬結果與實際量測資料的比較，修正模型，以期達到縮小精簡模型和實際IGZO TFTs之間的誤差。
並對此模型進行DC分析模擬以驗證模型中是否存在程式上的缺陷會使得模擬錯誤並討論模擬結果與實際資料之間的誤差原因；最後，當成DG a-IGZO TFT模型的修正完成後，透過HSPICE將此 DG TFT模型組成放大器電路，確認此模型在電路模擬上的表現，並討論其放大器電路模擬結果，分析電性表現。

In this thesis, the inverted staggered structure of TFTs with an etch stop layer (ESL) is chosen and a-IGZO is used as the material of active layers. We develop a compact model for this type of TFTs with double gates step by step. First, by referring to the journals, papers and books, the history of TFTs and information about them such as their architectures, the development of materials used as active layers is reviewed. The characteristics of a-IGZO is what we are interested in and its advantages and disadvantages will also be discussed. On the basis of suitable theories that we studied, the compact model for the single-gate a-IGZO TFT with the inverted staggered structure is developed, then HSPICE are used to call this compact model to do simulations. By comparing simulation results with measured data for the TFTs, parameters of the model are repeatedly revised until error rates between simulation results and measured data are small enough.
The intention for this thesis is to develop the compact model for double-gate TFT with inverted staggered structures. After finishing the single-gate TFT compact model with basic characteristics, one additional gate (Back Gate) is introduced to the original single-gate TFT structure. The role of this second gate is to adjust the threshold voltage of the TFT, which can give more room on designing circuits and applications of TFTs. Based upon the theories of double-gate fully depleted silicon-on-insulator MOSFETs (DG FD SOI MOSFETs), the influence of the back gate on electrical performances of TFTs is discussed. Under the consideration of the back gate, the single-gate TFT compact model is modified and calibrated by comparing simulation results of this model with measured data.
DC analysis simulations for the model are also done to check whether there is any bug in the Verilog-A code which may make simulations generate simulation errors. Reasons for error rates between simulation results and measured data are also discussed. Finally, after the a-IGZO double-gate TFT compact model is developed, it is used to compose an amplifier circuit by HSPICE to see whether it can work properly on circuit simulations. And the simulation results for electrical performances of this amplifier are discussed.

[1] W. Den Boer, Active matrix liquid crystal displays: fundamentals and applications. Elsevier, 2011.
[2] T. Scheffer and J. Nehring, "Supertwisted nematic (STN) liquid crystal displays," Annual review of materials science, vol. 27, no. 1, pp. 555-583, 1997.
[3] 莊東漢, 黃漢邦, 謝國煌, 蔡豐羽, 陳炳宏, and 鄭晃忠, 平面顯示器概論. 高立圖書公司, 2008.
[4] L. J. Edgar, "Method and apparatus for controlling electric currents," ed: Google Patents, 1930.
[5] P. K. Weimer, "The TFT a new thin-film transistor," Proceedings of the IRE, vol. 50, no. 6, pp. 1462-1469, 1962.
[6] W. E. Howard, "Thin Film Transistors—A Historical Perspective," Marcel Dekker, Inc., New York, NY, p. 1, 2003.
[7] T. Brody, J. A. Asars, and G. D. Dixon, "A 6× 6 inch 20 lines-per-inch liquid-crystal display panel," IEEE Transactions on Electron Devices, vol. 20, no. 11, pp. 995-1001, 1973.
[8] B. J. Lechner, F. Marlowe, E. Nester, and J. Tults, "Liquid crystal matrix displays," Proceedings of the IEEE, vol. 59, no. 11, pp. 1566-1579, 1971.
[9] A. Tixier-Mita et al., "Review on thin-film transistor technology, its applications, and possible new applications to biological cells," Japanese Journal of Applied Physics, vol. 55, no. 4S, p. 04EA08, 2016.
[10] P. Le Comber, W. Spear, and A. Ghaith, "Amorphous-silicon field-effect device and possible application," Electronics Letters, vol. 15, no. 6, pp. 179-181, 1979.
[11] W. Spear, P. Le Comber, S. Kinmond, and M. Brodsky, "Amorphous silicon p‐n junction," Applied Physics Letters, vol. 28, no. 2, pp. 105-107, 1976.
[12] S. Depp, A. Juliana, and B. Huth, "Polysilicon FET devices for large area input/output applications," in Electron Devices Meeting, 1980 International, 1980, pp. 703-706: IEEE.
[13] T. W. Little, H. Koike, K.-i. Takahara, T. Nakazawa, and H. Ohshima, "A 9.5 inch, 1.3 mega-pixel low temperature poly-Si TFT-LCD fabricated by SPC of very thin films and an ECR-CVD gate insulator," in Display Research Conference, 1991., Conference Record of the 1991 International, 1991, pp. 219-222: IEEE.
[14] F. Garnier, G. Horowitz, X. Peng, and D. Fichou, "An all‐organic" soft" thin film transistor with very high carrier mobility," Advanced Materials, vol. 2, no. 12, pp. 592-594, 1990.
[15] M. Prins et al., "A ferroelectric transparent thin‐film transistor," Applied Physics Letters, vol. 68, no. 25, pp. 3650-3652, 1996.
[16] M. J. Powell, "The physics of amorphous-silicon thin-film transistors," IEEE Transactions on Electron Devices, vol. 36, no. 12, pp. 2753-2763, 1989.
[17] R. Hoffman, B. J. Norris, and J. Wager, "ZnO-based transparent thin-film transistors," Applied Physics Letters, vol. 82, no. 5, pp. 733-735, 2003.
[18] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors," Nature, vol. 432, no. 7016, pp. 488-492, 2004.
[19] H. Hosono, M. Yasukawa, and H. Kawazoe, "Novel oxide amorphous semiconductors: transparent conducting amorphous oxides," Journal of non-crystalline solids, vol. 203, pp. 334-344, 1996.
[20] H. Hosono, "Transparent amorphous oxide semiconductors for flexible electronics," in Handbook of Transparent Conductors: Springer, 2011, pp. 459-487.
[21] K. Takechi, M. Nakata, T. Eguchi, H. Yamaguchi, and S. Kaneko, "Comparison of ultraviolet photo-field effects between hydrogenated amorphous silicon and amorphous InGaZnO4 thin-film transistors," Japanese Journal of Applied Physics, vol. 48, no. 1R, p. 010203, 2009.
[22] H. Hosono, "Ionic amorphous oxide semiconductors: Material design, carrier transport, and device application," Journal of Non-Crystalline Solids, vol. 352, no. 9, pp. 851-858, 2006.
[23] K. Nomura, A. Takagi, T. Kamiya, H. Ohta, M. Hirano, and H. Hosono, "Amorphous oxide semiconductors for high-performance flexible thin-film transistors," Japanese Journal of Applied Physics, vol. 45, no. 5S, p. 4303, 2006.
[24] Y. Taur and T. H. Ning, Fundamentals of modern VLSI devices. Cambridge university press, 2013.
[25] S. Lee et al., "Trap-limited and percolation conduction mechanisms in amorphous oxide semiconductor thin film transistors," Applied Physics Letters, vol. 98, no. 20, p. 203508, 2011.
[26] X. Cheng, S. Lee, G. Yao, and A. Nathan, "TFT compact modeling," Journal of Display Technology, vol. 12, no. 9, pp. 898-906, 2016.
[27] H.-K. Lim and J. G. Fossum, "Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET's," IEEE Transactions on Electron Devices, vol. 30, no. 10, pp. 1244-1251, 1983.