本論文主要研究高分子介電層中載子捕獲基(Charge trap sites)的分佈位置與有機記憶元件特性之相關性(Position-dependent)，實驗中利用聚亞醯胺(Polyimide，PI)與聚醯胺酸(Polyamic acid，PAA)兩種高分子介電材料為基材，透過化學反應修飾材料使分子鍵結上具有捕捉載子能力的極性官能基-羥基(hydroxyl group)，並與PI及PAA分子交互摻混形成混合溶液，利用材料極性的差異，透過調控旋轉塗佈成膜的製程參數來控制極性基在介電層中的位置，製作出具極性基的分子在薄膜表層(PI-20I)或底層(PI-20A)的高分子介電複合薄膜(composite film)，接著將此複合膜當成載子捕捉層，並使用本實驗室自行合成之N型半導體十三烷基駢苯衍生物(N,N′-ditridecylperylene-3,4,9,10- tetracarboxylic diimide，PTCDI-C13H27)做為主動層材料，製作成N型有機非揮發電晶體式記憶體(Organic non-volatile transistor-type memory，ONVM ) 。
經由薄膜表面能、原子力顯微鏡的分析結果可證實材料於成膜過程中確實有相分離的現象，在元件電特性的表現方面，無論以PI-20A或PI-20I高分子為載子捕捉層、所製作成的記憶元件均表現出良好的載子捕捉能力，當極性基分佈於薄膜底層其元件的記憶窗口為8.2V (PI-20A，製程轉速6000 r.p.m.)，而極性基分佈於薄膜表層時其記憶窗口為5.4V (PI-20I，製程轉速6000 r.p.m.)，造成此差異性的原因可從電導量測(conductance method)結果解釋，因載子捕捉層PI-20A表層極性基密度較低，故介面缺陷態位密度(τit)的維持時間較短，載子在清除操作時容易釋放回半導體層，故記憶窗口較大。雖然以PI-20I為捕捉層之元件記憶特性略差，但具極性基的分子主要分佈於薄膜表層，由電容-電壓(Capacitance-voltage characteristic)分析結果顯示，高轉速下成膜的高分子介電層PI-20I與半導體層所形成之介面其載子累積能力較佳，因施加閘極偏壓時、具極性基的分子會被誘導產生偶極矩(field-induced electric dipole)、增加半導體於介面累積電子電荷的能力，使輸出電流大幅提升且於轉換特性曲線上並無遲滯面積的產生。實驗最後利用光輔助記憶元件的操作，大幅提升元件的清除效能，其中PI-20I薄膜表層因極性官能基密度較高，故由電場誘導的偶極矩能使光場產生的激子更有效率的作用於元件，記憶窗口可達到63V，優於薄膜PI-20A所製作之元件(59.1V)，而元件於記憶保持能力上，經過長時間後仍能維持104的高低導電度態比值(on/off state ratio)。本研究驗證載子補捉層中極性官能基位置是主導記憶體元件的電特性及記憶特性的要素之一，並成功的利用光場大幅提升記憶體元件的記憶效能。

The relationship between the vertical distribution of carrier-trapping sites in polymer films and the electrical performance of organic N-type non-volatile transistor-type memory devices (ONVMs) was discussed in this study. Two kinds of polymer dielectrics (polyimide, PI) with polar functional groups were used as the charge-trapping layer and the gate-modification layer. PI-20A are charge-trap sites distributed at the bulk of the PI polymer, and PI-20I are charge-trap sites distributed near the surface of the PI films. The drain current of the ONVMs with PI-20I dielectrics was obviously enhanced compared with those of devices with PI-20A dielectrics. This result shows that the abundance of hydroxyl groups at the interface between polymer dielectric layer (PI-20I) and semiconductor layer causes large drain output currents on the devices, which is attributed to an enhanced channel conductance and an amount of accumulated charges by gate-filed induced electrical dipoles. The magnitude of the memory window of ONVMs with PI-20A dielectrics was much larger than those of PI-20I-modified memory devices, which resulted in low hydroxyl group density at the PI-20A/semiconductor interface and easy release of trapped carriers in the PIs during the erasing operation of ONVMs. The above results demonstrate that carriers trapped at different positions of charge-storing sites in the polymer layer causes different memory effects on devices. It provides an ideal route for designing the charge-trapping layer of non-volatile transistor memory devices.

[1] D. Kahng, and S. M Sze, “A floating gate and its application tomemory devices”, IEEE Trans. Electron Devices, 14, 629, 1967.
[2] S. Paydavosi, H. Abdu, G. J. Supran, and V. Bulovi´c, “Performance comparison of different organic molecular floating-gate memories”, IEEE Trans. on Nanotechnology, 10, 594, 2011.
[3] S. J. Kim, Y. S. Park, S. H. Lyu, and J. S. Lee, “Nonvolatile nano-floating gate memory devices based on pentacene semiconductors and organic tunneling insulator layers”, Appl. Phys. Lett., 96, 033302, 2010.
[4] J. D. Blauwe, “Nanocrystal nonvolatile memory fevices”, IEEE Trans. on Nanotechnology, 1, 72, 2002.
[5] M. H White, D.A. Adams, and J. Bu, “ On the go with SONOS “, Circuits and Devices Lett., 22, p.17, 2001.
[6] K. T. Chang, W.M. Chen, C. Swift, J. M. Higman, W. M. Paulson, and K. M.Chang, “A new SONOS memory using source-side injection for programming “, IEEE Electron Device Lett., 19, p.253, 1998.
[7] J. Bu, and M. H. White, “Effects of two-step high temperature deuterium annealson SONOS nonvolatile memory devices “, IEEE Electron Device Lett., 22, p.17, 2001.
[8] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “ Novel multi-bit SONOS type flash memory using a high-k charge trapping layer “, VLSI Symp. Tech. Dig. P.27, 2003.
[9] P. Xuan, M. She, B. Harteneck, A. Liddle, J. Bokor, and T. J. King, “FinFET sonos flash memory for embedded applications”, IEDM Tech. Dig., 609, 2003.
[10] B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, “NROM: A novel Localized trapping, 2-bit non-volatile memory cell “, IEEE Electron Device Lett., 21, p.543, 2000.
[11] J.J. Lee, and D. –L. Kwong, “Metal Nano-crystal Memory with High-K Tunneling Barrier for Improved Data Retention “, IEEE Trans. Electron Devices, 52, p507, 2005.
[12] T. H. Hou, C. Lee, V. Narayanan, U. Ganguly, and E. C. Kan, “ Design optimization of metal nanocrystal memory- Part I: nanocrystal array engineering “, IEEE Trans. Electron devices, 53, p.3095, 2006.
[13] S.Choi, S. Sl. Kim, M. Chang, H. Hwang, S. Jeon, C Kim, “ Highly thermally stable TiN nanocrystals as charge trapping sites for non-volatile memory device applications “, Appl. Phys. Lett., 86, p.123110, 2005.
[14] S. Choi, S. Sl. Kim, M. Chang, H. Hwang, S. Jeon, and C Kim, “ Highly thermally stable TiN nanocrystals as charge trapping sites for non-volatile memory device applications ”, Appl. Phys. Lett., 86, p.123110, 2005.
[15] R. Waser, “ Resistive non-volatile memory devices (Invited Paper) ”, Microelectronic Engineering, 86, p.1925, 2009.
[16] Y. C. Yang, F. Pan, Q. Liu, M. Liu, and F. Zeng, “ Fully room-temperature-fabricated nonvolatile resistive memory for ultrafast and high-density memory application ”, Nano Lett., 9, p.1636, 2009.
[17] Y. W. Dong, X. Ji, W. Xu, J. Q. Tang, and P. Guo, “ Resistive
Switching and Memory Effect Based on CuSCN Complex Layer Created Through Interface Reactions ”, Electrochem. Solid State Lett., 12, p.H54, 2009.
[18] L. P. Ma, J. Liu, and Y. Yang, “ Organic electrical bistable devices and rewritable memory cells ”, Appl. Phys. Lett., 80, p.2997, 2002.
[19] J. Ouyang, C. W. Chu, C. R. Szmanda, L. Ma, and Y. Yang, “ Programmable polymer thin film and non-volatile memory device ”, Nat. Mater., 3, p.918, 2004.
[20] Qi-Dan Linga, Der-Jang Liawb, Chunxiang Zhuc, Daniel Siu-Hung Chanc, En-Tang Kanga, Koon-Gee Neoha “Polymer electronic memories: Materials, devices and mechanisms”, Prog. Polym. Sci., 3, p.917, 2008.
[21] Baeg, Kang-Jun; Khim, Dongyoon; Kim, Juhwan, “High-Performance Top-Gated Organic Field-Effect Transistor Memory using Electrets for Monolithic Printed Flexible NAND Flash Memory ”, Adv. Func. Mater. , 22, 2915, 2012.
[22] M. H. Choi, B. S. Kim, and J. Jang, “High-Performance Flexible TFT Circuits Using TIPS Pentacene and Polymer Blend on Plastic”, IEEE Electron, 33, 11, 2012.
[23] P. Cosseddu, G. Tiddia, S. Milita, A. Bonfiglio, “Continuous tuning of the mechanical sensitivity of Pentacene OTFTs on flexible substrates: From strain sensors to deformable transistors”, Org. Electronic, 14, 206, 2013.
[24] C.-F. Sung, D. Kekuda, L. F. Chu, F.-C. Chen, S.-S. Cheng, Y.-Z. Lee, M.-C. Wu, C.-W. Chu, “Hybrid TiOx/fluoropolymer bi-layer dielectrics for low-voltage complementary inverters”, Org. Electronic, 11, 154 ,2010.
[25] G. Horowitz, “Organic Field-Effect Transistors”, Adv. Mater., 10, 368, 1998.
[26] B. Crone, A. Dodabalapur, Y.-Y. Lin, R. W. Filas, Z. Bao, A. LaDuca, R. Sarpeshkar, H. E. Katz and W. Li, “Large-scale complementary integrated circuits based on organic transistors”, Nature, 403, 521, 2000.
[27] C. D. Dimitrakopoulos and P. R. L. Malenfant, “Organic Thin Film Transistors for Large Area Electronics”, Adv. Mater., 14, 99, 2002.
[28] F. Barbe and C. R. Westgate, J. Phys. Chem. Solids 31 , 2679, 1970.
[29] F. Ebisawa, T. Kurokawa, and S. Nara, J. Appl. Phys. 54, 3255, 1983.
[30] M. L. Petrova, L. D. Rozenshtein, and Fiz. Tverd. Tela (Sov. Phys.-Solid State) 12, 961, 1970.
[31] H. Koezuka, A. Tsumura, and T. Ando, Synth. Met. 18, 699, 1987.
[32] A. Facchetti, M. H. Yoon, T. J. Marks, “Gate Dielectrics for Organic Field-Effect Transistors: New Opportunities for Organic Electronics”, Adv. Mater., 17, 1705, 2005.
[33] A. C. Mayer, M. L. Swiggers, C. J. Johnson, J. L. Mack, Z. T. Zhu, R. L. Headrick, G. G. Malliaras, in Thin Film Transistor Technologies (ED: Y. Kuo), Electrochemical Society, Pennington, NJ, p.288, 2002.
[34] S.M. Sze, “ Semiconductor Devices Physics and Technology 2nd edition ”, John Wiley & Sons INC., 2001.
[35] M. A. Lampert, “ Simplified Theory of Space-Charge-Limited Currents in an Insulator with Traps ”, Physical Review, 103, p.1648, 1956.
[36] K. J. Baeg, Y. Y. Noh, J. Ghim, S. J. Kang, H. Lee, and D. Y. Kim, “ Organic Non-Volatile Memory Based on Pentacene Field-Effect Transistors Using a Polymeric Gate Electret ”, Adv. Mater., 18, p.3179, 2006.
[37] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “ Flash Memory Cells-An Overview ”, Proceedings of The IEEE, 85, p.1248, 1997.
[38] Bo-Liang Yeh, Yu-Hao Chen and Liang-Yun,“Organic Nonvolatile
Memory Based on Low Voltage Organic Thin Film Transistors with
Polymer Gate Electrets”, J. Electron. Mater., 158 (3) H277-H280, 2011.
[39] Neaman, “Semiconductor Physics and devices : Basic Principles 3rd edition”, McGraw-Hill.,2003.
[40] H. Tada, A. E. Kumpel, R. E. Lathrop, J. B. Slanina, “Thermal expansion coefficient of polycrystalline silicon and silicon dioxide thin films at high temperatures”, Journal of Applied Physics, 87, 4189-4193, 2000.
[41] S. Tatemichi, M. Ichikawa, T. Koyama, and Y. Taniguchi,”High mobility n-type thin-film transistors based on N, N-ditridecyl perylene diimide with thermal treatments”, Appl. Phys. Lett. 89, 112108, 2006.
[42] Wei-Yang Chou, Tsung-Yeh Ho and Horng-Long Cheng,“Gate field induced ordered electric dipoles in a polymer dielectric for low-voltage operating organic thin-film transistors”,RSC Adv., 2013, 3, 20267, 2013.