研究生: |
陳重輝 CHen, Chung-Hui |
---|---|
論文名稱: |
應用金氧半相容製程研製高電壓與高性能射頻次微米被動元件 The Studies of High Performance Passive Devices with CMOS Compatible Technology for High Voltage and RF System Applications |
指導教授: |
方炎坤
Fang, Yean-Kuen |
學位類別: |
博士 Doctor |
系所名稱: |
電機資訊學院 - 微電子工程研究所 Institute of Microelectronics |
論文出版年: | 2003 |
畢業學年度: | 91 |
語文別: | 英文 |
論文頁數: | 97 |
中文關鍵詞: | 被動元件 、空氣柱內連接線 、金氧半導體 、多晶矽電阻 、高頻率 、晶片電感 、高電壓 、靜電防護元件 |
外文關鍵詞: | Passive Device, high voltage, CMOS, air-gap, ESD protection, interconnection, on-chip inductor, polysilicon resistor, high frequency |
相關次數: | 點閱:107 下載:20 |
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本論文探討應用次微米金氧半導體相容製程研製高電壓及高性能射頻被動元件的特性, 並提出改善的製程技術。研究的被動元件類型包括多晶矽電阻, 高Q值電感, 低介電系數內連接線與具低負載電容的靜電防護元件。
吾人對高電壓金氧半製程的多晶矽電阻提出三個方法來改善多晶矽電阻的線性度: (A) 利用植入氮離子法填補晶格邊界中的缺陷與在多晶矽的表面形成一層薄薄的氮化矽以防止後續的電漿輔助化學汽相沉積中的氫入侵; (B)在多晶矽的金屬接觸窗之下形成較薄的場二氧化矽以吸收橫向的砷離子, 防止砷在多晶矽中的單晶與單晶之間的晶格邊界離析; (C)建立直流電流加壓改善線性度的準則, 使離析的磷離子來填補晶格邊界中的缺陷; 藉由這三個方法, 可以降低高電壓電阻的TCR, VCR 與 匹配參數, 並藉以改善線性度。其次,吾人利用金氧半標準製程中的打線金屬視窗清除製程, 並以特製的濕式蝕刻劑來除去包圍晶片電感的介電材料, 使得從晶片電感到矽基板的能量損失降低, 進而增加晶片電感的品質參數; 除此之外,更以有限元素分析法來設計更穩定的懸空晶片電感結構及以二極體-堆疊n型金氧半電晶體結構, 對需要高電壓低負載電容的類比與高頻輸出入電路提供靜電防護。最後,對於銅製程金屬的內連接線, 吾人也提出一個利用銅導線及空氣柱為介電係數的新結構及製程。
The characteristics of passive devices with submicron CMOS compatible technology for high voltage and RF system applications have been investigated. Additionally, some advanced technologies have been developed to promote the characteristics of the developed passive devices. For high voltage polysilicon resistor, we use, (A) the nitrogen implantation to form a thin SiN layer on the top of the polysilicon resistor to prevent the hydrogen intrusion caused by the final passivation PECVD SiN from affecting the linearity of resistivity; (B) the thin oxide layer underneath the resistor to absorb the lateral arsenic dopant that was implanted to form the ohmic contact between the tungsten contact and the polysilicon. Because of the arsenic dopant segregate in the grain boundaries will deteriorate the voltage coefficient ratio of resistance (VCR) and the temperature coefficient ratio (TCR). (C) The optimization of DC current stress trimming for the high voltage polysilicon resistor under high current stress. With these technologies, the TCR, VCR, matching and the linearity of the resistivity of the high voltage polysilicon resistor are improved significantly.
Next, for radio-frequency on-chip suspended spiral inductor, the oxide between the silicon substrate and the aluminum wire is removed by the CMOS process compatible post-processing wet-etch to reduce the substrate coupling loss and raise the quality factor as well as the self-resonance frequency. On the design of the suspended inductors we use the finite-element method simulation to analyze the mechanical stability. Furthermore, the diode-stacked NMOS device with only 250fF parasitic capacitance has been developed to protect the thin gate oxide of the 0.18um CMOS for high voltage and high frequency input-output circuits during the electro-static-discharge (ESD). Finally, we also propose a new scheme of copper interconnection with air-gap.
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