經驗模態分解(empirical mode decomposition, EMD)和局域均值分解(local mean decomposition, LMD)，是已被廣泛應用在分析非線性系統與非穩態訊號的高效能訊號分解方法。EMD和LMD的計算過程耗費大量運算，想透過軟體來實現高速的EMD或LMD運算是非常困難的。
在本論文中，我們提出了EMD和LMD的硬體設計與實現。我們首先提出了一個有彈性、低成本、高效能的EMD矽智財核心。這個矽智財核心可以達成眾多EMD應用所需的高速條件要求。在我們的設計裡，EMD矽智財的所有變數都已盡可能參數化。使用我們提出的EMD SIP Generator輔助系統，使用者可自行選取不同參數來讓各種不同的EMD應用使用，相對應的Verilog電路會根據使用者的選擇自動產生、並可以輕鬆整合進其他硬體系統裡。實驗結果顯示，我們所提出的EMD電路與既有的EMD設計相比，所需硬體成本較低、執行速度也較快。
接著，本論文也提出了一個高速LMD硬體架構。因為已良好的參數化，我們所提出的LMD電路可以輕鬆被整合進各種不同的LMD應用或硬體架構裡。使用者可自行挑選最適合他的應用的參數來使用。分解結果顯示，我們所提出的LMD設計不僅有彈性、成本低、速度快，在精確度表現上也很不錯。
本論文所有的硬體設計都使用Verilog硬體描述語言設計開發、都使用Synopsys公司的Design Compiler合成工具及TSMC的標準元件庫合成電路、並且都可以輕鬆整合進各種不同應用與硬體架構。依據合成結果，我們提出的設計在硬體成本與速度上皆具極佳的競爭力。

Empirical mode decomposition (EMD) and local mean decomposition (LMD) are effective signal decomposition methods widely used for analyzing nonlinear systems and nonstationary signals. The sifting processes of EMD and LMD require intensive computations. Achieving high-speed EMD or LMD calculations by using software solutions are difficult.
In this dissertation, the hardware implementations of EMD and LMD are pre-sented. First, a flexible, low-cost, and high-performance silicon intellectual prop-erty (SIP) core for EMD is proposed to meet the high-speed requirements of vari-ous EMD applications. Variables in the proposed EMD SIP are parameterized as much as possible. By using the proposed auxiliary software system, the EMD SIP Generator, users can choose various parameters for different EMD applications. The corresponding Verilog code will be automatically generated according to a user’s settings and can be easily embedded into other hardware systems. Experi-mental results show that the proposed EMD circuit requires lower hardware cost and achieves higher working speed as compared with previous EMD designs.
Second, a high-speed hardware architecture for LMD is proposed in this dis-sertation. With the help of parameterization, the proposed LMD circuit can be eas-ily used for various applications and hardware architectures. Users can choose the most closely coincident result for various LMD applications. The decomposition results show that the proposed designs are not only flexible, fast, and low-cost, but also have satisfactory precision.
All proposed circuits were developed using Verilog and then synthesized us-ing the Synopsys Design Compiler with the Taiwan Semiconductor Manufacturing Company (TSMC) cell libraries, and these circuits can be easily used for various applications and hardware architectures. The synthesis results demonstrate that the proposed designs have the advantages of low-cost and high-performance.

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