在本論文中，佈局參數效應及淺溝槽絕緣製程對45奈米N型金氧半場效電晶體的特性被深入的探討。首先，金氧半場效電晶體受單軸應力影響造成載子移動率上升的物理機制被研究到，且數種應用在互補式金氧半場效電晶體由製程而產生的應變矽科技也被討論到。
接下來，研究的是佈局參數對奈米尺寸N型金氧半場效電晶體的影響。研究指出元件的尺寸對於奈米尺寸的N型金氧半場效電晶體的表現有較明顯的影響，主要是因為在通道區域經由各種製程所產生的單軸應力，包括淺溝槽絕緣、金屬矽化物和接觸孔洞蝕刻停止層，會隨著元件尺寸的改變而有所變動。並且我們發現由淺溝槽絕緣製程所造成的應力在元件的寬度及源極汲極長度縮減到0.1微米以下後扮演了一個相當重要的角色，且會造成N型金氧半場效電晶體表現較明顯的減益。
最後，我們提出並且研究一個改善過的緻密化製成應用在利用次大氣壓化學氣相沉積所生成的淺溝槽絕緣，用以減少由淺溝槽絕緣所造成的壓縮應力並進一步的提升N型金氧半場效電晶體的效能。從導通電流能夠很清楚的看到改善過的製程其效能比起標準製程要來的好。並且這個藉由製程改變所得到的效能增益會隨著元件作用區的縮減而有所增加，這表示了這個製程改變是很適用在目前45奈米科技以及以後更先進的製程，只要是元件具有較小的作用區。

In this thesis, the effects of device layouts and Shallow Trench Isolation (STI) processes on the performance of advanced 45-nm technology NMOSFETs are investigated. First, the physic mechanisms of the carrier mobility enhancement for MOSFETs under uniaxial stress are studied, and various process-induced strained Si technologies used in nanoscale CMOS devices are discussed.
Next, the layout dependences of nanoscale NMOSFETs are studied. It is shown that device dimensions have a significant influence on the nanoscale NMOSFET performance because the uniaxial stress in the channel region generated by various processes, including STI, silicide, and CESL, would change as the device dimensions change. Furthermore, STI-induced stress is found to play a major role and significantly degrade NMOSFET performance as device width and source/drain length shrink down to 0.1 um regime.
Lastly, we present and investigate an improved densification process for SACVD-based STI to reduce STI-induced compressive stress and to boost NMOSFET performance in 45-nm technology node. It is found that the on-current (Ion) of NMOS devices with the improved STI process is effectively enhanced as compared to the devices with Standard process. In addition, the Ion enhancements significantly increase with scaling down the device width and source/drain length, implying that the improved STI process is very suitable to be adopted in the 45-nm nodes and beyond, where device structures have small active area.

Chapter 1
[1.1] S. M. Sze, Physics of Semiconductor Devices. New Jersey: John Wiley & Sons, p.91, 1981.
[1.2] N. Mohta and S. E. Thompson, “Mobility enhancement,” IEEE Circuits & Devices Magazine, vol. 21, p. 18, Sep. 2005.
[1.3] S. Takagi, T. Irisawa, T. Tezuka, T. Numata, S. Nakaharai, N. Hirashita, Y. Moriyama, K. Usuda, E. Toyoda, S. Dissanayake, M. Shichijo, R. Nakane, S. Sugahara, M. Takenaka, and N. Sugiyama, “Carrier-transport-enhanced channel CMOS for improved power consumption and performance,” IEEE Trans. Electron Devices, vol. 55, p. 21, Jan. 2008.
[1.4] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H. S. Philip Wong, “Device scaling limits of Si MOSFETs and their application dependencies,” in Proc. of the IEEE, vol. 89, p. 259, 2001.
[1.5] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits,” in Proc. of IEEE, vol. 91, p. 305, 2003.
[1.6] H. Shang, M. M. Frank, E. P. Gusev, J. O. Chu, S. W. Bedell, K. W. Guarini, and M. Leong, “Germanium channel MOSFETs: opportunities and challenges,” IBM J. Res. and Dev., vol. 50, p. 377, Jul./Sep. 2006.
[1.7] J. S. Goo, Q. Xiang, Y. Takamura, F. Arasnia, E. N. Paton, P. Besser, J. Pan, and M. R. Lin, “Band offset induced threshold variation in strained-strained-Si nMOSFETs,” IEEE Electron Device Lett., vol. 24, no. 9, p. 568, Sep. 2003.
[1.8] J. S. Rieh, D. Greenberg, A. Stricker, and G. Freeman, “Scaling of SiGe heterojunction bipolar transistors,” in Proc. of the IEEE, vol. 93, p. 1522, 2005.
[1.9] International Technology Roadmap for Semiconductors (ITRS), Semiconductor Ind. Assoc., 2005.
[1.10] C. W. Liu, S. Maikap, and C. Y. Yu, “Mobility-inhancement technologies,” IEEE circuits & Devices, vol. 21, p. 21, May 2005.
[1.11] K. Rim, K. Chan, L. Shi, D. Boyd, J. Ott, N. Klymko, F. Cardone, L. Tai, S. Koester, M. Cobb, D. Candaperi, B. To, E. Duch, I. Babich, R. Carruthers, P. Saunders, G. Walker, Y. Zhang, M. Steen , and M. Ieong, “Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs,” in IEDM Tech. Dig., p. 49, 2003.
[1.12] S. I. Takagi, J. L. Hoyt, J. J. Welser, and J. F. Gibbons, “Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal oxide semiconductor field-effect transistors,” J. Appl. Phys., vol. 80, p. 1567, Aug. 1996.
[1.13] W. Zhang, and J. G. Fossum, “On the threshold voltage of strained-Si/Si1-xGex MOSFETs,” IEEE Trans. Electron Devices, vol. 52, p. 263, Feb. 2005.
[1.14] C. H. Ge, C. C. Lin, C. H. Ko, C. C. Huang, Y. C. Huang, B. W. Chan, B. C. Perng, C. C. Sheu, P. Y. Tsai, L. G. Yao, C. L. Wu, T. L . Lee, C. J. Chen, C. T. Wang, S. C. Lin, Y. C. Yeo, and C. Hu, “Process-strained Si (PSS) CMOS technology featuring 3D strain engineering,” in IEDM Tech. Dig., p. 73, 2003.
[1.15] S. E. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, “Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs,” in IEDM Tech. Dig., p. 221, 2004.
[1.16] S. E. Thompson, and et al., “A 90-nm logic technology featuring strained-silicon,” IEEE Trans. Electron Devices , vol. 51, p. 1790, Nov. 2004.
[1.17] T. Y. Lu, and T. S. Chao, “Mobility enhancement in local strain channel nMOSFETs by stacked a-Si/poly-si gate and capping nitride,” IEEE Electron Device Lett., vol. 26, no. 4, p. 267, Apr. 2005.
[1.18] C. H. Chen, T. L. Lee, T. H. Hou, C. L. Chen, C. C. Chen, J. W. Hsu, K. L. Cheng, Y. H. Chiu, H. J. Tao, Y. Jin, C. H. Diaz, S. C. Chen, and M. S. Liang, “Stress Memorization Technique (SMT) by Selectively Strained-Nitride Capping for Sub-65nm High-Performance Strained-Si Device Application,” IEEE VLSI Tech. Dig., p. 56, 2004.

Chapter 2
[2.1] S. I. Takagi, J. L. Hoyt, J. J. Welser, and J. F. Gibbons, “Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 80, p. 1567, Aug. 1996.
[2.2] Y. Sun, S. E. Thompson, and T. Nishida, “Physics of strain effects in
semiconductors and metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 101, p. 1045, May 2007.
[2.3] N. Mohta, and S. E. Thompson, “Mobility Enhancement,” IEEE Circuits and Devices Magazine, vol. 21, p. 18, Sep. 2005.
[2.4] K. Uchida, T. Krishnamohan, K. C. Saraswat, and Y. Nishi, “Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime,” in IEDM Tech. Dig., p. 129, 2005.
[2.5] H. Irie, K. Kita, K. Kyuno, and A. Toriumi, “In-plane mobility anisotropy and universality under uni-axial strains in n- and p-MOS inversion layers on (100), (110), and (111) Si,” in IEDM Tech. Dig., p. 225, 2004.
[2.6] S. I. Takagi, J. Koga, and A. Toriumi, “Subband structure engineering for performance enhancement of Si MOSFETs,” in IEDM Tech. Dig., p. 219, 1997.
[2.7] S. E. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, “Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs,” in IEDM Tech. Dig., p. 221, 2004.
[2.8] L. Smith, V. Moroz, G. Eneman, P. Verheyen, F. Nouri, L. Washington, M. Jurczak,O. Penzin, D. Pramanik, and K. D. Meyer, “Exploring the limits ofstress-enhanced hole mobility,” IEEE Electron Device Lett., vol. 26, no. 9, p.652, Sep. 2005.
[2.9] X. Yang, Y. Choi, T. Nishida, and S. E. Thompson, “Gate direct tunneling currents in uniaxial stressed MOSFETs,” in Proc. of Int. EDST, p. 149, 2007.
[2.10] V. Chan, K. Rim, M. Ieong, S. Yang, R. Malik, W. T. Young, M. Yang, Q. Ouyang, “Strain for CMOS performance improvement,” IEEE CICC., p. 667, 2005.
[2.11] J. A. Bandur and H. B. Pogge, 1978, US Patent, 4 104086.
[2.12] A. Bryant, W. Hansch and T. Mil, “Characteristics of CMOS device isolation for ULSI age,” in IEDM Tech. Dig., p. 671, 1994.
[2.13] M. H. Juang, C. L. Chen and S. L. Jang, “Study of shallow trench isolation technology with a poly-Si sidewall buffer layer,” in Semicond. Sci. Technol., p. 1, 2008.
[2.14] M. Miyamoto, H. Ohta, Y. Kumagai, Y. Sonobe, K. Ishibashi, and Y. Tainaka, “Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics,” in IEEE Tran. Electron Devices, vol. 51, no. 3, March 2004.
[2.15] R. Arghavani, Z. Yuan, N. Ingle, K-B Jung, M. Seamons, S. Venkataraman, V. Banthia, K. Lilja, P. Leon, G. Karunasiri, S. Yoon, and A. Mascarenhas, “Stress management in sub-90-nm transistor architecture,” in IEEE Tran. Electron Devices, vol. 51, no. 10, Oct. 2004.
[2.16] Y. Jeon, G.C. F. Yeap, P. Grudowski, T. Van Gompel, J. Schmidt, M. Hall, B. Melnick, M. Mendicino, S. Venkatesan, “The impact of STI mechanical stress on the device performance of 90 nm technology node with different substrates and isolation processes,” IEEE VLSI Tech. Dig., p. 164, 2003.
[2.17] Y. Li, H. M. Chen, S. M. Yu, J. R. Hwang, and F. L. Yang, “Strained CMOS devices with shallow-trench-isolation stress buffer layers,” in IEEE Tran. Electron Devices, vol. 55, no. 4, April 2008.
[2.18] C. Le Cam, F. Guyader, C. de Buttet, P. Guyader, G. Ribes, M. Sardo, S. Vanbergue, F. Boeuf, F. Arnaud, E. Josse, M. Haond, “A low cost drive current enhancement technique using shallow trench isolation induced stress for 45-nm node,” in IEEE VLSI Tech. Dig., p. 1, 2006.
[2.19] A. T. Tilke, C. Stapelmann, M. Eller, K. H. Bach, R. Hampp, R. Lindsay, R. Conti, W. Wille, R. Jaiswal, M. Galiano, and A. Jain, “Shallow trench isolation for the 45-nm CMOS node and geometry dependence of STI stress on CMOS device performance,” in IEEE Tran. Semi. Manu., vol. 20, no. 2, May 2007.
[2.20] A. Steegen, K. Maex, I. D. Wolf, “Local mechanical stress induced defects for Ti and Co/Ti silicidation in sub-0.25um MOS-technologies,” in IEEE VLSI Tech. Dig., p. 98, 1998.
[2.21] A. Steegen, K. Maex, “Silicide-induced stress in Si: origin and consequences for MOS technologies,” in Mater. Sci. and Eng. R, p. 1, 2002.
[2.22] Y. Luo and D. K. Nayak, “Enhancement of CMOS performance by process-induced stress,” in IEEE Tran. Semi. Manuf., vol. 18, no. 1, Feb. 2005.
[2.23] X. Chen, S. Fang, W. Gao, T. Dyer, Y. W. The, S. S. Tan, Y. Ko, C. Baiocco, A. Ajmera, J. Park, J. Kim, R. Stierstorfer, D. Chidambarrao, Z. Luo, N. Nivo, P. Nguyen, J. Yuan, S. Panda, O. Kwon, N. Edleman, T. Tjoa, J. Widodo, M. Belyansky, M. Sherony, R. Amos, H. Ng, M. Hierlemann, D. Coolbough, A. Steegen, I. Yang, J. Sudijono, T. Schiml, J. H. Ku, C. Davis, “Stress proximity Technique for performance improvement with dual stress liner at 45nm technology and beyond,” in IEEE VLSI Tech. Dig., p. 6, 2006.
[2.24] S. Orain, V. Fiori, D. Villanueva, A. Dray, and C. Ortolland, “Method for managing the stress due to the strained nitride capping layer in MOS transistors,” in IEEE Tran. Electron Devices, vol. 54, no. 4, April 2007.
[2.25] M. H. Liao, L. Yeh, T. L. Lee, C. W. Liu, M. S. Liang, “Superior n-MOSFET performance by optimal stress design,” in IEEE Elec. Dev. Lett., vol. 29, no. 4, April 2008.
[2.26] C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, R. Gwoziecki, S. Orain, E. RObilliart, C. Raynaud, and H. Dansas, “Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress,” in IEEE Tran. Electron Devices, vol. 51, no. 8, Aug. 2004.
[2.27] P. W. Liu, W. T. Chiang, Y. T. Huang, T. L. Tsai, C. H. Tsai, C. T. Tsai, and G. H. Ma, “Improved layout dependence in high performance SiGe channel CMOSFETs,” in IEEE VLSI Tech. Dig., p. 8, 2008.
[2.28] R. Li, L. Yu, H. Xin, Y. Dong, K. Tao and C. Wang, “A comprehensive study of reducing the STI mechanical stress effect on channel-width-dependence Idsat,” in Semi. Sci. and Tech., p. 1292, 2007.

Chapter 3
[3.1] S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, T. Numata, K. Usuda, Y. Moriyama, S. Nakaharai, and M. Koga, “Channel structure design, fabrication and carrier transport properties of strained-Si / SiGe-On- Insulator (Strained-SOI) MOSFET,” in IEDM Tech. Dig., pp. 57-60, 2003.
[3.2] S. L. Wu, Y. M. Lin, S. J. Chang, S. C. Lu, P. S. Chen, and C. W. Liu, “Enhanced CMOS performances using substrate strained-SiGe and mechanical strained-Si technology,” IEEE Ele. Dev. Lett., vol. 27, no. 1, Jan. 2006.
[3.3] M. Ozturk, N. Pesovic, I. Kang, J. Liu, H. Mo, and S. Gannavaram,“Ultra-shallow source/drain junctions for nanoscale CMOS using selective silicon-germanium technology,” in Proc. Int. Workshop on Junction Technology, vol. 77, 2001.
[3.4] A. Eiho, T. Sanuki, E. Morifuji, T. Iwamoto, G. Sudo, K. Fukasaku, K. Ota, T. Sawada, O. Fuji, H. Nii, M. Togo, K. Ohno, K. Yoshida, H. Tsuda, T. Ito, Y. Shiozaki, N. Fuji, H. Yamazaki, M. Nakazawa, S. Iwasa, S. Muramatsu, K. Nagaoka, M. Iwai, M. Ikeda, M, Saito, H. Naruse, Y. Enomoto, Kitano, S. Yamada , K. Imai, N. Nagashima, T. Kuwata, F. Matsuoka, “Management of Power and Performance with Stress Memorization Technique for 45nm CMOS,” in IEEE VLSI Tech. Dig., p. 218, 2007.
[3.5] S. Pidin, T. Mori, RNakamura, T. Saiki, R. Tanabe', S. Satoh, M. Kase, K. Hashmoto, and T. Sugii, “MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node,” in IEEE VLSI Tech. Dig., p. 54, June 2004.
[3.6] A. Bryant, W. Hansch, and T. Mii, “Characteristics of CMOS device isolation for the ULSI age,” in Tech. Dig. Int. Electron Devices Meet., p. 671, 1004.
[3.7] A. T. Tilke, C. Stapelmann, M. Eller, K. H. Bach, R. Hampp, R. Lindsay, R. Conti, W. Wille, R. Jaiswal, M. Galiano, and A. Jain, “Shallow trench isolation for the 45-nm CMOS node and geometry dependence of STI stress on CMOS device performance,” in IEEE Tran. Semi. Manuf., vol. 20, no. 2, May 2007.
[3.8] R. Arghavani, Z. Yuan, N. Ingle, K-B Jung, M. Seamons, S. Venkataraman, V. Banthia, K. Lilja, P. Leon, G. Karunasiri, S. Yoon, and A. Mascarenhas, “Stress management in sub-90-nm transistor architecture,” IEEE Trans. Electron Devices, vol. 51, no. 10, p. 1740, Oct. 2004

Chapter 4
[4.1] H. N. Lin, H. W. Chen, C. H. Ko, C. H. Ge, H. C. Lin, T. Y. Huang, and W. C. Lee,“Correlating drain-current with strain-induced mobility in nanoscale strained CMOSFETs,” IEEE Electron Device Lett., vol. 27, no. 8, p. 659, Aug. 2006.
[4.2] Y. Kanda, “A graphical representation of the piezoresistance coefficients in silicon,” IEEE Trans. Electron Devices, vol. 29, p. 64, Jan. 1982.
[4.3] Y. Luo, D. K. Nayak, “Enhancement of CMOS performance by process-induced stress,” in IEEE Tran. Semi. Manuf., vol. 18, no. 1. Feb. 2005.
[4.4] G. Eneman, M. Jurczak, P. Verheyen, T. Hoffmann, A. De Keersgieter and K. De Meyer, “Scalability of strained nitride capping layers for future CMOS generations,” in Proc. of ESSDERC, p. 449, 2005.
[4.5] K. W. Su, Y. M. Sheu, C. K. Lin, S. J. Yang, W. J. Liang, X. Xi, C. S. Chiang, J. K. Her, Y. T. Chia, C. H. Diaz, and C. Hu, “A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics,” IEEE Custom Integrated Cir. Conf., p. 245, 2003.
[4.6] Y. J. Yang, M. H. Liao, C. W. Liu, L. Yeh, T. L. Lee, and M. S. Liang, “Superior n-MOSFET performance by optimal stress design,” in IEEE ISDRS, p. 97, Dec. 2007.
[4.7] A. Steegen, K. Maex, “Silicide-induced stress in Si: origin and consequences for MOS technologies,” in Mater. Sci. and Eng. R, p. 1, 2002.
[4.8] M. Stadele, G. Ilicali, E. Landgraf, M. Goldbach, S. Finsterbusch, J. Lindolf, J. Radechker, B. Uhlig, “Reduction of layout variations with stress-compensated hybrid STI fills: a comprehensive analysis,” in IEEE VLSI Tech. Dig., p. 71, 2008.

Chapter 5
[5.1] S. E. Thompson, G. Sun, Y. S. Choi, and T. Nishida, “Uniaxial-process-induced strained-Si: extending the CMOS roadmap,” in IEEE Tran. Electron Devices, vol. 53, no. 5, May 2006.
[5.2] J. Amon, A. Kieslich, L. Heineck, T. Schuster J. Faul, J. Luetzen, C. Fan, C. C. Huang, B. Fischer, G. Enders, S. Kudelka, U. Schroeder, K. H. Kuesters , G. Lange, J. Alsmeier, “A highly manufacturable deep trench based DRAM cell layout with a planar array device in a 70nm technology,” in IEDM Tech. Dig., p. 73, 2004.
[5.3] C. Le Cam, F. Guyader, C. de Buttet, P. Guyader, G. Ribes, M. Sardo, S. Vanbergue, F. Boeuf, F. Arnaud, E. Josse, M. Haond, “A low cost drive current enhancement technique using shallow trench isolation induced stress for 45-nm node,” in IEEE VLSI Tech. Dig., p. 1, 2006.
[5.4] T. Irisawa, T. Numata, T. Tezuka, K. Usuda, N. Sugiyama, and S. I. Takagi, “Device design and electron transport properties of uniaxially strained-SOI tri-gate nMOSFETs,” in IEEE Tran. Electron Devices, vol. 55, no. 2, Feb. 2008.
[5.5] P. Hashemi, L. Gomez, and Judy L. Hoyt, “Gate-all-around n-MOSFETs with uniaxial tensile strain-induced performance enhancement scalable to sub-10-nm nanowire diameter,” in IEEE Electron Device Lett., vol. 30, no. 4, April 2009.
[5.6] C. Y. Hsieh, Y. T. Lin, and M. J. Chen, “Distinguishing between STI stress and delta width in gate direct tunneling current of narrow n-MOSFETs,” in IEEE Electron Devices, p. 1, 2009.