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研究生: 林家葦
Lin, Jia-Wei
論文名稱: 具動態輸入截斷的高精度近似乘法器
A High Accuracy Approximate Multiplier With Dynamic Input Truncation
指導教授: 林英超
Lin, Ing-Chao
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年: 2021
畢業學年度: 109
語文別: 英文
論文頁數: 43
中文關鍵詞: 近似計算 、乘法器 、可動態調整乘法器 、捲積神經網路
外文關鍵詞: Approximate Computing, Multiplier, adjustable multiplier, CNN
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  • 乘法器是許多領域 (像是機器學習、影像處理以及數位訊號處理) 不可或缺的運 算單元。而在這些應用通常都會使用大量的乘法運算,而導致高功耗。為了降低功 耗,近似乘法器被許多研究提出。近似乘法器是一種犧牲準確度以換取減少功耗、 面積以及提高速度的乘法器。而在機器學習、影像處理以及數位訊號處理有著可以 容錯的特性,也就是說在這些領域所需要的計算結果不需要完全準確。因此近似乘 法器很適合應用在這些領域。
    在本論文中,我們提出了一種高精度的近似 4­2 壓縮器,可以用來快速的壓縮 部份乘積。我們還根據所提出的高精度的近似 4­2 壓縮器去設計一個簡單的誤差補 償電路來減少誤差。此外為了使得我們所提出的乘法器可以根據當下的需求去動態 的調整所需的準確度,我們提出了動態輸入截斷方法。實驗結果顯示,與華萊士樹 乘法器 (Wallace Tree Multiplier) 相比,我們所提出的可動態調整近似乘法器的延遲可 以降低 27%,並且平均功耗可以降低 40.33%(高達 72%)。此外,我們在 case study 章節會去探討之前的乘法器以及我們所提出的可動態調整近似乘法器應用在卷積神 經網路上的效果。

    Multipliers are among the most critical arithmetic functional units in many applications, and those applications commonly require many multiplications which result in significant power consumption. For applications that have error tolerance, an approximate multiplier is an emerging method to reduce critical path delay and power consumption. An approx­ imate multiplier can trade off accuracy for lower energy and higher performance. In this paper, we propose an approximate 4­2 compressor with high accuracy. In addition to the proposed approximate 4­2 compressor, we propose an adjustable approximate multiplier that can dynamically truncate partial products to achieve variable accuracy requirements. We also propose a simple error compensation circuit to reduce error distance. The proposed approx­ imate multiplier can adjust the accuracy or bit­width of multiplication at run­time based on the users'requirement. Experimental results show that the delay of the proposed adjustable approximate multiplier can be reduced by 27% and the average power consumption of the proposed multiplier can be reduced by 40.33% (up to 72%) when compared to the Wallace tree multiplier. Moreover, we demonstrate that our proposed multiplier can be suitable for a convolutional neural network to meet different requirements at each layer.

    摘要i Abstract ii Table of Contents iii List of Tables v List of Figures vi Chapter 1. Introduction 1 Chapter 2. Preliminaries 4 2.1 Wallace Tree Multiplier 4 2.2 Approximate Multiplier Design Approaches 5 2.3 Approximate 4-2 Compressor 9 2.4 Adjustable Approximate Multiplier 12 2.5 Evaluation Metrics 13 Chapter 3. Method 15 3.1 Proposed Flow and Approximate Multiplier 15 3.2 Proposed High-Accuracy 4-2 Compressor 16 3.3 Dynamic Input Truncation 20 3.4 Proposed Approximate Multiplier 22 Chapter 4. Experimental Setup and Result 25 4.1 Experimental Setup 25 4.2 Accuracy Comparison 27 4.3 Timing Delay Comparison 29 4.4 Area Comparison 30 4.5 Power Comparison 30 4.6 Comparison of Dynamic Input Truncation and Programmable Truncation 31 Chapter 5. Case-Study 33 5.1 Experimental Setup 33 5.2 Quantization 34 5.3 CNN Application 35 5.4 Result Discussion 38 Chapter 6. Conclusion and Future Work 41 References 42

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