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研究生：	洪仕勳 Hung, Shih-hsun
論文名稱：	多核心處理器連結網路介面之設計與實現 Design and Implementation of a Network Interface for Multi-Core System
指導教授：	陳培殷 Chen, Pei-Yin
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Department of Computer Science and Information Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	中文
論文頁數：	42
中文關鍵詞：	網路介面、硬體實作、晶片網路
外文關鍵詞：	hardware implementation, network interface, NoC, network-on-chip
相關次數：	點閱：99 下載：2
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隨著半導體工業的快速進步，愈來愈多的電晶體能被置入於一個單一的晶片上，因此單晶片系統 (System-On-Chip) 成為現今晶片設計的主要重點。早期的單晶片系統當中，主要是憑藉匯流排來連接各個矽智財 (IP) 模組。在這種傳輸模式之下，傳輸資料的延遲、電路的同步、雜訊的產生和功率消耗的問題，也隨著製程的增進而更需要去重視。隨著單顆晶片內可擺放電晶體總數目的急遽增加，傳統的匯流排傳輸已經漸漸地不敷使用，為了確保各模組之間資料傳送和訊號溝通的正確性，有人提出利用現行電腦網路所使用的封包(packet)傳送觀念來進行不同矽智財 (IP) 模組間的資料交換。這種將單晶片系統內部的傳輸介面轉換成由網路模式傳輸的方式，稱為晶片網路（network-on-chip, NoC）設計。
本論文中，首先討論晶片網路內所包含的元件與模組。而為了使處理器能有更好的效率，我們設計了一個擁有簡易直接記憶體存取 (direct memory access，DMA) 的網路介面 (network interface)。在系統裡，每一筆資料的傳送接收，都會由作業系統發出適當的中斷訊號來通知處理器，而為了增加處理器的資料處理效率，在網路介面中設計了類似直接記憶體存取的模組。處理器只需要在確定要接收傳送此資料時，通知網路介面此筆資料在記憶體中的位址和長度，網路介面會自行讀取下一筆的資料而不需要中斷處理器的執行，以期能提升處理器的使用效能。我們所設計的電路是使用TSMC 0.18μm 標準元件庫來合成與實現，在此製程下可以達到 100 MHZ 的運作速度。

With the evolution of semiconductor technology, more and more transistors can be put into a single chip. System-On-Chip has become an important technique. Most of the current communication architectures in SoC are based on dedicated wires or buses. The problems of data delay, synchronization, noise, signal reliability, and power dissipation in bus communication are far more serious when more and more transistors are put into a single chip. In order to ensure the validity of data transfer and communication in SoC, the packet-switched network which delivers message between communicating components is a potential solution. That kind of architecture is called Network-on-chip (NoC).
In the thesis, we have discussed the possible modules or components in the NoC. In order to obtain better efficiency, we have designed a network interface with simple direct memory access. Operating system will send the interrupt to the processor for every transfer or receive data. To increase the processor performance, we design a DMA-like module in the network interface. As long as the processor wants to transfer or receive the data, it needs to send the memory address and data length to network interface only. Network interface will read or write data by itself and without cutting off the processor, thus the effective utilization of the processor can be improved. The VLSI architecture is designed with Verilog and implemented with TSMC 0.18μm cell library. In the simulation, it can operate at 100 MHz properly.

中文摘要................................................................................................................................ I
Abstract...............................................................................................................................II
誌謝.................................................................................................................................... III
目錄.................................................................................................................................... IV
圖目錄................................................................................................................................ VI
表目錄...............................................................................................................................VIII
第一章 緒論......................................................................................................................... 1
1.1 研究背景及動機.................................................................................................... 1
1.2 論文組織................................................................................................................ 3
第二章 網路晶片(Network On Chip).................................................................................. 4
2.1 連網設計................................................................................................................ 4
2.2 NoC 架構............................................................................................................. 6
2.3 網路介面.............................................................................................................. 13
2.4 其他網路介面...................................................................................................... 16
第三章 所提出的網路介面架構....................................................................................... 19
3.1 AMBA 介紹....................................................................................................... 19
3.2 SDMA 的資料處理.............................................................................................. 22
3.3 資料傳遞.............................................................................................................. 24
3.4 網路介面整體架構.............................................................................................. 29
第四章 硬體架構及實作................................................................................................... 32
4.1 硬體運作流程...................................................................................................... 32
4.2 內部模組的設計.................................................................................................. 34
4.2.1 匯流排轉換器（Bus Transactor）........................................................... 34
4.2.2 網路介面控制器（Network Interface Controller） ................................ 35
4.2.3 資料傳送控制器（Data Sender Controller）.......................................... 37
4.2.4 資料接收控制器（Data Receiver Controller）..................................... 38
4.2.5 簡易直接記憶體存取控制器（SDMA Controller）.............................. 39
4.3 電路實作.............................................................................................................. 40
結論.................................................................................................................................... 41
參考文獻............................................................................................................................. 42
                                    

[1] AMBA Bus specification, http://www.arm.com, 1999.
[2] Wishbone Service Center, http://www.silicore.net/wishbone. htm, 2004.
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[5] E. Bolotin et al. QNoC: QoS architecture and design process for network on chip. Journal of Systems Architecture, 49, Dec. 2003.
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[8] S. Kumar et al. A network on chip architecture and design methodology. In Proc. ISVLSI, 2002.
[9] L. Benini and D. Bertozzi, “Xpipes: A Network-on-Chip Architecture for Gigascale Systems-on-Chip,” IEEE Circuits and Systems Magazine, vol. 4, no. 2, pp. 18-31, 2004
[10] P. Bhojwani and R. Mahapatra. Core network interface architecture and latency constrained on-chip communication. In Proc. of Int. Symp. on Quality Electronic Design (ISQED), 2006.

校內：2018-08-26公開
校外：2018-08-26公開

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