晶圓級封裝相較於傳統打線製程封裝有較小尺寸、較佳電性及較低製造成本等優點，因此被廣泛應用於攜帶性電子產品。封裝體上板後進行溫度循環測試時，由於矽晶片與印刷電路板間之熱膨脹係數不匹配，銲錫接點在溫度循環時承受的熱應力將導致其發生疲勞破壞；銅佈線之疲勞破裂以及介電薄膜在銅墊片周圍處之裂紋成長亦為可能之失效模式。因此，WLP技術發展的重要任務為透過幾何及材料參數之最佳化，提升封裝在溫度循環下之可靠度。
　　本文針對0.5 mm錫球間距、100個銲錫接點之WLP進行以類神經網路為基礎之結構最佳化設計。考慮之設計參數包括凸塊結構、錫球材料、銅墊片直徑、介電薄膜厚度以及凸塊下金屬層厚度，並利用全因子設計法規劃參數之實驗配置。為了進行封裝之可靠度評估，以三維之非線性有限元素模擬計算錫球之塑性功密度增量、銅佈線之塑性應變範圍以及介電薄膜之第一主應力作為評估指標。其中所使用之類神經網路以有限元素分析所得之數據訓練後，以其為目標函數進行多目標遺傳演算法運算，搜尋提升WLP結構可靠度之最佳參數組合。本研究所得之結果可作為改進WLP結構可靠度之設計參考，並可將所使用之系統化流程延伸應用於其他電子封裝產品之可靠度分析。

Wafer level package (WLP) has advantages such as smaller size, higher electrical performance and lower fabrication cost compared to conventional wirebond package, and is widely used in portable electronic applications. Because of the thermal expansion mismatch between the silicon chip and the laminate printed circuit board, thermal stresses under temperature cycling are likely to induce solder joint fatigue fracture. In addition, the redistribution layer (RDL) Cu trace fatigue cracking and the polymeric dielectric cracking around pad are also possible failure modes of WLP under board-level temperature cycling. Consequently, an important task in developing WLP technology is to perform materials and geometry optimization for temperature cycling reliability.
In this thesis, an artificial neural network (ANN) based design optimization for a 0.5 mm-pitch 100-I/O WLP is presented. Design variables including bump pad configuration, solder alloy composition, Cu pad diameter, RDL polymer dielectric thickness and pad opening diameter, and under-bump Cu thickness are grouped and considered by using 3-level full factorial designs. Key indices including inelastic strain energy density increment, equivalent plastic strain increment, and maximum principle stress corresponding to solder joint fatigue fracture, RDL trace fatigue fracture and polymer dielectric cracking, respectively, are estimated by using numerical finite element (FE) simulations.
A back-propagation ANN is first constructed and trained by the indices calculated from the three-dimensional nonlinear FE analyses. By setting the trained ANN models for the failure indices as objective functions, a multi-objective genetic algorithm is then applied for determining the optimal solutions for WLP materials and geometry. The systematic approach developed in this study for the WLP design optimization can also be applied to consider other package type or loading conditions.

[1]江國寧, “微電子系統封裝基礎理論與應用技術,” 滄海書局, 2006.
[2]WLP examples: Connectivity chip from ST.
http://www.i-micronews.com/upload/Micronews/images/Yole%20WLP%20market%20products%202009.jpg
[3]鄧上軒, 擴散型晶圓級封裝之翹曲研究, 國立成功大學機械工程學系碩士論文, 2009.
[4]R. Darveaux, “Effect of simulation methodology on solder joint crack growth correlation,” Proceedings of the 50th Electronic Components and Technology Conference, pp. 1048-1058, 2000.
[5]J. H. Lau, S.-W. R. Lee and C. Chang, “Solder joint reliability of wafer level chip scale packages (WLCSP): A time-temperature-dependent creep analysis,” Journal of Electronic Packaging, Vol. 122, pp. 311-316, 2000.
[6]X. Zhang, V. Kripesh, T. C. Chai, T. C. Tan, D. Pinjala and M. K. Iyer, “Parametric design and solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP),” Proceedings of the 2005 Electronic Packaging Technology Conference, pp. 158-162, 2005.
[7]J.-C. Lin, H.-C. Cheng and K.-N. Chiang, “Design and analysis of wafer-level CSP with a double-pad structure,” IEEE Transaction on Advanced Packaging Technologies, Vol. 28, pp. 117-126, 2005.
[8]M. C. Yew, C. Yuan, C. N. Han, C. S. Huang, W. K. Yang and K. N. Chiang, “Factorial analysis of chip-on-metal WLCSP technology with fan-out capability,” Proceedings of the 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, pp. 223-228, 2006.
[9]C.-C. Lee, S.-M. Chang and K.-N. Chiang, “Sensitivity design of DL-WLCSP using DOE with factorial analysis technology,” IEEE Transaction on Advanced Packaging Technologies, Vol. 30, pp. 44-55, 2007.
[10]R. H. Hong and J. Wang, “Board level WLCSP 3D thermal stress analysis by submodeling of FEA,” Proceedings of the 11th International Conference on Electronic Packaging Technology & High Density Packaging, pp. 762-766, 2010.
[11]Y.-B. Park, R. Mönig and C. A. Volkert, “Thermal fatigue as a possible failure mechanism in copper interconnects,” Thin Solid Films, Vol. 504, pp. 321-324, 2006.
[12]D. T. Read, “Tension-tension fatigue of copper thin films,” International Journal of Fatigue, Vol. 20, No. 3, pp. 203-209, 1998.
[13]R. Schwaiger, G. Dehm and O. Kraft, “Cyclic deformation of polycrystalline Cu films,” Philosophical Magazine Letters, Vol. 83, pp. 693-710, 2003.
[14]G. P. Zhang, C. A. Volkert, R. Schwaiger, E. Arzt and O. Kraft, “Damage behavior of 200-nm thin copper films under cyclic loading,” Journal of Materials Research, Vol. 20, pp. 201-207, 2005.
[15]J.-H. Park, J.-H. An, Y.-J. Kim, Y.-H. Huh and H.-J. Lee, “Tensile and high cycle fatigue test of copper thin film,” Materials Science and Engineering Technology, Vol. 39, pp. 187-192, 2008.
[16]N. Murata, K. Tamakawa, K. Suzuki and H. Miura, “Fatigue strength of electroplated copper thin films under uni-axial stress,” Proceedings of the Electronic Materials and Packaging 2008 International Conference, pp. 41-44, 2008.
[17]O. Kraft, R. Schwaiger and P. Wellner, “Fatigue in thin films: lifetime and damage formation,” Materials Science and Engineering: A, Vol. 319, pp. 919-923, 2001.
[18]Y. Xiang, X. Chen and J. J. Vlassak, “The mechanical properties of electroplated Cu thin films measured by means of the bulge test technique,” Materials Research Society Symposium Proceedings, Vol. 695, pp.189-196, 2002.
[19]G. P. Zhang, R. Schwaiger, C. A. Volkert and O. Kraft, “Effect of film thickness and grain size on fatigue-induced dislocation structures in Cu thin films,” Philosophical Magazine Letters, Vol. 83, pp. 477-483, 2003.
[20]X. J. Sun, C. C. Wang, J. Zhang, G. Liu, G. J. Zhang and X. D. Ding, “Thickness dependent fatigue life at microcrack nucleation for metal thin films on flexible substrates,” Journal of Physics D: Applied Physics, Vol. 41, p. 195404, 2008.
[21]D. Wang, C. A. Volkert and O. Kraft, “Effect of length scale on fatigue life and damage formation in thin Cu films,” Materials Science and Engineering: A, Vol. 493, pp. 267-273, 2008.
[22]Y. Hwangbo and J.-H. Song, “Fatigue life and plastic deformation behavior of electrodeposited copper thin films,” Materials Science and Engineering: A, Vol. 527, 2010.
[23]Y. Hwangbo and J.-H. Song, “Plastic deformation behavior analysis of an electrodeposited copper thin film under fatigue loading,” International Journal of Fatigue, Vol. 33, pp.1175-1181, 2011.
[24]C.-I. Ho, T.-C. Hung and C.-I. Hung, “Thermal analysis and optimization for a ball grid array package,” Proceedings of the Institution of Mechanical Engineers, Part C: Journal of Mechanical Engineering Science, Vol. 219, pp. 381-393, 2005.
[25]L. Zhang, G. Subbarayan, B. B. Hunter and D. Rose, “Response surface models for efficient, modular estimation of solder joint reliability in area array packages,” Microelectronics Reliability, Vol. 45, pp. 623-635, 2006.
[26]R. C. Law and I. A. Azid, “Application of artificial neural network in thermal and solder joint reliability analysis for stacked dies LBGA,” Proceedings of the 33rd International Electronics Manufacturing Technology Conference, pp. 1-7, 2008.
[27]M. Variyam, T.-C. Chiu, V. Sundararaman and D. Edwards, “Effect of package and board characteristics on solder joint reliability of MicroStar BGA,” Proceedings of the 53rd Electronic Components and Technology Conference, pp. 583-588, 2003.
[28]范栩, 結構最佳化遺傳演算之類神經網路近似法, 國立台灣大學工學院機械工程學系碩士論文, 2007.
[29]羅華強, 類神經網路—MATLAB的應用, 高立圖書, 2011.
[30]M. T. Hagan, H. B. Demuth and M. Beale, Neural Network Design, PWS Pub. Co., 1996.
[31]MATLAB, R2012a, MathWorks, Inc., 2012.
[32]K. Hornik, “Multilayer feedforward networks are universal approximators,” Neural Networks, Vol. 2, pp. 359-366, 1989.
[33]K. Hornik, “Approximation capabilities of multilayer feedforward networks,” Neural Networks, Vol. 4, pp. 251-257, 1991.
[34]D. J. C. MacKay, “Bayesian interpolation,” Neural Computation, Vol. 4, No. 3, pp. 415-447, 1992.
[35]J. H. Holland, Adaptation in Natural and Artificial Systems, MIT Press, 1975.
[36]林昇甫, 徐永吉, 遺傳演算法及其應用, 五南圖書, 2009.
[37]簡亞倫, 在演算法階層藉由多目標基因演算法以降低能量消耗導向之硬體分割方法, 國立成功大學電機工程研究所碩士論文, 2008.
[38]K. Deb, Multi-Objective Optimization using Evolutionary Algorithms, John Wiley & Sons, Ltd., 2001.
[39]P. L. Yu, “A class of solutions for group decision problems,” Management Science, Vol. 19, pp. 936-946, 1973.
[40]毛昭陽, 以最佳等效錫球觀念修正子模型分析法進行疊晶球柵陣列構裝錫球可靠度之最佳化分析, 國立成功大學工程科學系博士論文, 2008.
[41]ANSYS, Release 14.0, ANSYS, Inc., 2011.
[42]D. Bhate, D. Chan, G. Subbarayan, T. C. Chiu, V. Gupta and D. Edwards, “Constitutive behavior of Sn3.8Ag0.7Cu and Sn1.0Ag0.5Cu alloy at creep and low strain rate regimes,” IEEE Transactions on Components and Packaging Technologies, Vol. 31, pp. 622-633, 2008.