隨著科技日新月異，電腦已經可以幫助人們完成相當多事情，更進一步的，我們希望電腦可以模擬人類的視覺，能夠自動辨識或分析資料，我們稱為此為電腦視覺。在電腦視覺的領域中，行人偵測一直都是一個重要的研究議題，它被廣泛用於一些生活應用上，舉凡監視系統與行車安全系統等，皆是仰賴行人偵測來達到保障人身安全的目的，故準確的行人偵測演算法可以大大提升這些系統的實用性。局部二值模式(LBP)是一個強健的特徵擷取演算法，它可以有效的描述待測物件的紋理特徵，相較於其他的特徵擷取演算法，局部二值模式(LBP)在行人偵測的研究上有著相當優異的效果。
因行人偵測技術可能有用於嵌入式裝置的需求，例如行車記錄器等，故我們提出了一個近似的方法，來取代原演算法中運算較複雜，且硬體難以實現的部分，例如開根號與三角函數運算等，並使用Verilog硬體描述語言實做成電路，來減少整體的運算時間，以達到即時的行人偵測效果。同時我們根據Soft-IP的方式，讓使用者可以根據自己的需求，自由的調整演算法中的參數，來產生不同的硬體電路。
我們將局部二值模式之硬體架構分為8級管線化電路。並使用SYNOPSYS Design Compiler 及 TSMC 0.13μm標準元件來合成，合成結果顯示此電路由12.3k個邏輯閘數(Gate Counts)組成，工作頻率(Clock Frequency)可達500MHz，吞吐量(Througputs)為平均每秒可以處理268M個像素，並擁有約95%以上的行人偵測準確度。

With the advancement in technology, computer vision is now the achieving goal where computers can imitate human vision and can help identifying and analyzing data automatically. In computer vision, human detection has been an important research topic, which can be widely used in many applications in ensuring human safety, such as surveillance systems and automotive systems. Therefore, high accuracy human detection algorithm can greatly enhance the practicability of these systems. Local Binary Pattern (LBP) is a robust feature extraction algorithm. It can efficiently describe the text features of the target object. As compared to other feature extraction algorithm, Local Binary Pattern (LBP) has excellent achievement in the researches of human detection.
Since human detection technique are performed in embedded devices to make applications practical, such as dashboard cameras, the hardware approximation technique is used to propose an approximate method to replace the complex computations like trigonometric functions and square roots in this thesis. The hardware architecture of the proposed design is implemented to decrease the computation time of the system so that it can reach real-time human detection processing. Meanwhile, the Soft-IP methodology is also used in designing the hardware. Users are able to adjust the parameters to generate different hardware design to meet their needs.
Our proposed design is an 8-stage pipelined hardware architecture, synthesized with SYNOPSYS Design Compiler in the TSMC 0.13μm cell library. It is made of 12.3k gate counts, and achieves a clock frequency of 500MHz. The throughputs are able to process 268M pixels per second. The accuracy rate for human detection is regularly higher than 95% on average.

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