| 研究生: |
解昇維 Chieh, Seng-wei |
|---|---|
| 論文名稱: |
VC-1解碼器於PAC DSP 3.0之實作研究 Implementation of VC-1 Decoder on PAC DSP 3.0 |
| 指導教授: |
楊家輝
Yang, Jar-ferr |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering |
| 論文出版年: | 2007 |
| 畢業學年度: | 95 |
| 語文別: | 中文 |
| 論文頁數: | 100 |
| 中文關鍵詞: | 整數離散餘弦轉換 、VC-1解碼器 、去方塊效應濾波器 、動態預測補償 |
| 外文關鍵詞: | VC-1 Decoder, Integer Discrete Cosine Transform, Motion Compensation, De-blocking filter |
| 相關次數: | 點閱:127 下載:1 |
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VC-1是由全球軟體界的知名廠商微軟公司在2003年發表之自主開發的動態影像壓縮技術,其壓縮技術整合了MPEG及H.264之優點,壓縮率逼近於H.264,但卻有複雜度更低之優點。因此,電影及電視學會(SMPTE)已採用為視訊壓縮標準,於娛樂影視工業將有機會取代H.264成為的視訊壓縮之主流。
PAC DSP為工研院晶片發展中心自行研發的DSP晶片,適用於各種多媒體行動裝置,它特殊的架構以及獨厚的效能非常適合於開發極度複雜演算法的實現,為國內第一顆在雙核心處理器設計上擁有自主權的32位元數位訊號處理器晶片。
本論文將研究VC-1視訊壓縮解碼及後處理技術於PAC DSP之實現技術,其中研究整數離散餘弦轉換、動態預測補償、反量化相關之快速演算法於PAC DSP之實現為研究重點,同時我們利用程式技巧結合演算法,完成即時VC-1視訊壓縮解碼軟體。
VC-1 video compression standard was announced by the global well-known software company, Microsoft Corporation in 2003. The VC-1 video compression integrates MPEG and H.264 technologies to achieve nearly coding efficient as H.264 but with much lower complexity. The VC-1, which has been accepted by the Society of Motion Picture and Television Engineering (SMPTE) as the video standard, could very possibly replace H.264 as the major video coding standard in motion picture and television industries.
The Parallel Architecture Core (PAC) with digital signal processing (DSP) capability developed by SoC Technology Center, Industrial Technology Research Institute (ITRI) is a potential DSP chip, which is suitable for development of mobile multimedia devices. Designed with high efficiency special architecture, the PAC DSP as the first 32-bit processor core developed in Taiwan provides many opportunities for realization of multimedia applications with sophisticate algorithms.
In this thesis, we study the realization techniques of VC-1 decoder and its postprocessing technologies in the PAC DSP. The researches focus on the fast implementation algorithms of integer inverse discrete cosine transformation, motion compensation, inverse quantization in the PAC DSP. In the same time, the real-time VC-1 decoder software with some programming techniques is also suggested to achieve a real-time VC-1 decoder realized in the PAC DSP.
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