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研究生: 李軍鑫
Lee, Chun-Hsin
論文名稱: 應變矽鍺P型場效電晶體元件電性及低頻雜訊特性之研究
Investigation of strained SiGe Field-Effect Transistor on DC and 1/f Noise Characteristics
指導教授: 吳三連
Wu, San-Lein
張守進
Chang, Shoou-Jinn
學位類別: 博士
Doctor
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2007
畢業學年度: 95
語文別: 英文
論文頁數: 103
中文關鍵詞: 金半場效電晶體矽鍺負偏壓溫度效應金氧半場效電晶體乾式蝕刻
外文關鍵詞: SiGe, Dry Etching, MESFETs, NBTI, MOSFETs
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  • 本論文中,我們主要研究利用固體源分子束磊晶法,與超高真空化學氣相沉積法,成長矽鍺/矽異質接面場效電晶體結構對電晶體元件電特性與雜訊分析。並各種結構進行能帶工程以及載子分佈理論模擬分析。
    在實驗製作方面,首先利用四氟化碳和氯氣及惰性氣體氬氣於電感耦合電漿蝕刻對矽鍺材料做蝕刻特性探討。接著應用乾式蝕刻技術應用於應變矽鍺通道摻雜金半場效電晶體的製作,由實驗結果得知電晶體有較低漏電流,且也有著較佳的汲極電流與轉導特性。我們試著探討使用不同矽鍺通道含量的金氧半場效電晶體的的電特性與1/f雜訊特性,引入漸變式矽鍺通道可改善元件的電特性與低頻雜訊。最後探討矽鍺元件的可靠度分析。可靠度分析中的負偏壓溫度效應主要是電洞打斷矽與二氧化矽介面的矽氫鍵結,產生介面陷阱並進而影響元件的臨限電壓。由於應變矽鍺元件會將大部分的電洞載子侷限在埋藏通道中,降低矽與二氧化矽介面的濃度。因此矽鍺P型場效電晶體有較小的負偏壓溫度不穩定性效應。也較適合之後的積體電路使用。

    This thesis analyzes the performance of SiGe hetero FETs grown using solid-source molecular beam epitaxy (SS-MBE) or ultra high vacuum chemical vapor deposition (UHV-CVD). The simulation of band engineering and carrier distribution for the devices was also conducted.
    We report the experimental realization of SiGe/Si materials using the CF4/Ar and Cl2/Ar mixed-gas inductively coupled plasma (ICP) etching process. The ICP process was applied to the fabrication of SiGe doped-channel field-effect transistors based on etch characteristics. Compared to device fabricating using wet etching mesa, the doped-channel FET using the ICP mesa shown a higher breakdown voltage, a lower leakage current, a higher transconductance, and a larger on/off current ration due to the elimination of most parasitic current paths between isolated devices. The DC characteristics and 1/f noise of the strained SiGe PMOSFET with an inversely Ge-graded profile and with a constant Ge profile in the channels are measured and compared. Finally, the negative bias temperature instability (NBTI) effect on SiGe devices is investigated. The NBTI effect is mainly caused by the breaking of Si-H bonds by a hot hole at the Si/SiO2 interface, generating interface traps which affect the threshold voltage. By introducing a strained SiGe layer in a PMOSFET, the holes are primarily located in the SiGe channel due to the valence band offset and thus the hole concentration in the Si surface channel is lower than that of the control Si PMOSFET. Therefore, SiGe PMOSFETs have a lower NBTI effect than control Si devices. The experimental results show that SiGe devices are a better choice for future ULSI technology.

    Abstract(Chinese) i Abstract(English) iii Acknowledgements v Table Captions ixx Figure Captions x Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization 3 Chapter 2 Characteristics of Strained Si1-xGex Heterostructures 5 2.1 Properties of the Si/Si1-xGex Epitaxial Layer 5 2.2 Band Diagram of the Sil-xGex/Si System 6 2.3 Transport Properties of Strained SiGe or Strained Si 9 Chapter 3 Inductively Coupled Plasma Etching of Si1-xGex in CF4/Ar and Cl2/Ar Discharges 22 3.1 Introduction 22 3.2 Description of ICP 23 3.4 Results and Discussion 25 3.5 Summary 27 Chapter 4 Improved Performance of SiGe Doped-Channel Field-Effect Transistors Using Inductively Coupled Plasma Etching 38 4.1 Introduction 38 4.2 Fabrication of SiGe-based Doped-Channel Field-Effect Transistors 40 4.3 Results and Discussion 42 4.4 Summary 44 Chapter 5 The DC and 1/f Noise Characteristics of Strained SiGe PMOSFETs 53 5.1 Motive and 1/f background thesis of Strained SiGe PMOSFETs 53 5.2 SiGe PMOSFETs with a Graded Ge Content Channel Profile 59 5.3 DC characteristics 63 5.4 1/f Noise Results and Discussion 65 Chapter 6 Negative Bias Temperature Instability Immunity 80 6.1 Introduction 80 6.2 Description of NBTI 81 6.3 Experiment Setup 83 6.4 Results and Discussion 84 6.5 Summary 86 Chapter 7 Conclusion and Future Work 93 7.1 Conclusion 93 7.2 Future Work 94 Reference 96

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