扇出型晶圓級封裝是現今異質整合的一個主要技術，此封裝是由良裸晶粒、環氧樹酯封膠、重分佈層所組成，重分佈層中金屬導線材料以銅金屬薄膜為為主。扇出型晶圓級封裝之優勢包括：低成本、高性能、高接腳數。然而隨著現今積體電路中電晶體密度上升，封裝中重分佈層線寬線距不斷縮小，重分佈層也需要多層堆疊，這些使用上的可靠度仍然備受挑戰。基於上述需求，本論文的目標為建立細銅線之黏塑性本構模型，並將其應用於電子封裝可靠度分析。
目前在重分佈層中最小的線寬及線距分別約為2 µm及2 µm，為了分析在此尺度下銅線之可靠度，本文的目的是以實驗方法量測扇出型晶圓級封裝中銅線之本構行為，並建立對應之黏塑性本構模型，並將此黏塑性本構模型應用於封裝板階熱循環模擬，分析扇出型晶圓級封裝中之多層重分佈層中銅金屬塑性變形的累積，並探討幾何參數改變對結構受熱循環負載之可靠度之影響。
由實驗結果發現，相較於相近厚度的銅薄膜材料，銅線具有較高的降伏應力以及較低的延性。由實驗研究所建立之銅線亞蘭德黏塑性本構模型與實驗結果吻合。將此模型應用於扇出型晶圓級封裝之可靠度分析，模擬發現減少扇出型晶圓級封裝中重分佈層層數及減小矽晶尺寸可提升銅佈線可靠度，而矽晶厚度則需減小至0.1 mm才可明顯提升銅佈線之可靠度。

Copper has been widely used in integrated circuit (IC) because of its excellent electrical and thermal properties. It is well known that the mechanical properties of Cu are affected by factors such as the dimension, grain size and method of deposition. This study investigated the mechanical constitutive behavior of Cu traces with 2-µm width and 2-µm spacing, which is the representative dimensions used in redistribution layer (RDL). From the experimental characterizations, it was shown that the Cu trace exhibits higher yielding stress than the Cu thin film of similar thickness does, and the value of elongation at rupture of the Cu trace is lower than that of the Cu thin film. By post-processing the experimental characterization results obtained in this study, the corresponding Anand viscoplastic model constants were estimated. The viscoplastic model was then implemented in finite element (FE) models to consider the risk of reliability failure of a fan-out wafer-level packaging (FOWLP) containing multi-layered RDL under board-level temperature cycling (T/C) test. From the simulation results it can be concluded that better T/C reliability can be achieved by decreasing Si die size and thickness, and that by decreasing the number of metal layers in the RDL improves the Cu trace reliability, but degrades the solder joint reliability.

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