在射頻接收器前端電路中，混頻器是一重要元件，其將來自低雜訊放大器的高頻訊號轉換成低頻訊號，提供給後級的數位電路所使用。在RFIC電路的設計課題中，可以發現混頻器的雜訊和線性度對於整個射頻接收器前端電路是相當重要的。

在2~11GHz的應用頻帶中，有多個不同標準的無線通訊系統，包含了WLAN、UWB和WiMAX。在本篇論文中，將提出數個射頻混頻器之設計，包含以下三個電路：應用於3.1~10.6GHz低功率高增益平坦度超寬頻混頻器、應用於3.1~10.6GHz高線性超寬頻混頻器、以及2.4/5.2GHz 共電流雙頻混頻器。

在3.1~10.6GHz低功率高增益平坦度超寬頻混頻器設計中，提供多個單頻的外接式巴倫，達到全頻帶的差動輸入訊號。並採用反向器當作LO埠的開關，使其達到低電流損耗。

在3.1~10.6GHz高線性超寬頻混頻器中，延續前者的核心架構，提供寬頻晶片型的巴倫取代多個單頻的外接式巴倫，可以減少晶片外的不確定寄生效應，例如：鎊線、SMA接頭、PCB板連接…等因素。並且使量測環境簡易化，進一步達到晶片單一化。

在2.4/5.2GHz 共電流雙頻混頻器中，雜訊來自頻帶中和頻帶外的干擾透過元件的非線性機制會污染所需頻帶的訊號，並且會退化電路的雜訊指數和線性度，為了減輕其退化，兩個抑制干擾的雙頻機制運用在此電路中。

本篇論文之電路設計是以TSMC 0.18um CMOS製程之model進行模擬，並透過CIC申請下線，完成晶片之製作

In radio frequency receiver front-end, mixer is an important component. Mixer can translate high frequency signal from low noise amplifier into low frequency signal for base-band system. In the course of design of the RFICs, it was found that its noise and linearity performances are important for the performance of the receiver.

There are a lot of different standards of wireless communication systems operating in 2~11GHz, including WLAN, UWB and WiMAX. In this thesis, we designed three radio frequency mixers which contain a low-power high gain-flatness CMOS switched transconductor UWB mixer, a high linearity of CMOS switch transconductor UWB mixer with on-chip baluns and a dual-band concurrent mixer with on-chip baluns for multi-standard applications.

In the first design, in order to provide input differential signal of overall band in UWB system, several single-frequency outer baluns are used. For LO port, inverters are taken as switch to achieve low power consumption.

In the second design, heritage core circuit of the former design, several single-frequency baluns are replaced by wideband on-chip balun which can reduce uncertain parasitic effect of off-chip, such as bonding wire, SMA connection and the connection of PCB boards. With on-chip balun can make the measurement more convenient and reach our chip simplification.

In the third design, the noises from in-band or out-of-band interferences will contaminate signals of desired bands through nonlinearity mechanism of devices and degrade the circuit performances of noise figure and linearity. In order to alleviate the degradation, two dual-band circuit topologies are used to suppress the interferences in this design.

With EM simulation, the influence of lines in the layout can be considered. The circuits are implemented by TSMC 0.18um CMOS process. These chips have also been fabricated by the support of CIC in Taiwan.

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