簡易檢索 / 詳目顯示

回結果列表
研究生： 吳宗翰
Wu, Zong-Han
論文名稱： N型通道金氧半電晶體於不同操作狀態下生命週期之預測
Lifetime Prediction Under Different Operation Mode In NMOSFET
指導教授： 陳志方
Chen, Jone-Fang
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年： 2018
畢業學年度： 106
語文別： 英文
論文頁數： 65
中文關鍵詞： 低壓金氧半場效電晶體 、熱載子導致之退化 、電腦輔助設計模擬 、生命週期
外文關鍵詞： LVMOSFET, hot-carrier-induced degradation, TCAD simulation, Lifetime
相關次數： 點閱：239  下載：9 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 本論文主要在探討低壓(LV)金氧半場效電晶體(MOSFET)元件在不同操作區域中退化之物理機制以及其退化後之生命週期。
    首先，描述研究動機，並介紹前人之研究成果與實驗，將藉由短時間量測推斷出長時間退化曲線，以及元件生命週期之公式推導，並加以應用在不同元件上，並延伸研究，以符合所使用之元件之生命週期。本論文會介紹元件退化機制、熱載子效應等影響元件可靠度之議題，亦會介紹所引用的生命週期預測之基本論述，並搭配分析元件特性之電腦輔助設計(TCAD)模擬軟體。
    簡介後，將會介紹所採用元件結構以及其基本特性，並介紹本研究之實驗設置，包括 On State、Off State 到 Subthreshold之電壓設置及量測方法介紹。
    本研究的內容，主要想探討實驗之元件在On state、Off state和 Subthreshold三區之退化，並且搭配電腦輔助設計(TCAD)模擬軟體來推測可能之物理機制。
    而進一步探究是否可以藉由短時間之量測，推算出長時間之退化曲線。並且配合造成元件退化之原因，推測出可能造成退化之公式，進一步寫成生命週期之公式。並且配合元件特性，以及長時間之退化曲線，進一步修改成吻合所採用元件之真實的生命周期，也加以證實了退化曲線平移後所獲得的長時間退化曲線可以和生命週期之估算吻合。另外也得平移退化曲線之方法僅適用於到同樣的退化物理機制。

    In the thesis, the low voltage MOSFET degradation mechanism and lifetime prediction in different operation region had been investigated.
    First of all, in motivation, the previous work in earlier research had been introduced. In previous work, the long term degradation trend obtained from short time measuring, and derived lifetime equation had been public. Hence, in this work, the concept was used in practice to derived the lifetime equation in another device and found that if the equation fit with actual lifetime in our device. Also the degradation mechanism and the reliability issues like hot carrier injection, impact ionization, gate induced drain leakage will also be introduced. Moreover, TCAD simulation will also be introduced and assisted us to diagnosed the mechanism.
    In chapter two, the structure and characteristic of our device will introduced, after that, the experiment setup in on state, subthreshold and off state will also introduced.
    According to the degradation mechanism we analyzed, the parameter of lifetime equation can be curtained, thus through the basic method and some modification, the lifetime equation of our device could be obtained.

    中文摘要 I Abstract III 致謝 V Content VI Table Captions VIII Figure Captions IX Chapter 1 1 1-1 Motivation of the thesis 1 1-2 Introduction of LV devices applications 2 1-3 Introduction of scaling factor 2 1-4 Introduction of time equation prediction 4 1-5 Introduction of hot carrier reliability 4 1-6 Introduction of technology computer aid design 6 1-7 About the thesis 8 Chapter 2 14 2-1 Introduction 14 2-2 Device structure description 14 2-3 Measurement methodology 15 2-3-1 Measurement setup 15 2-3-2 ID-VD measurement 15 2-3-3 ID-VG measurement 16 2-3-4 Isub-VG measurement 16 2-3-5 VBD measurement 17 2-4 Summary 18 Chapter 3 24 3-1 Introduction 24 3-2 The hot carrier stress methodology 24 3-3 On state stress induced degradation discussion 25 3-4 Off state stress induced degradation discussion 26 3-5 Subthreshold stress induced degradation discussion 27 3-6 Summary 28 Chapter 4 40 4-1 Introduction 40 4-2 Scaling factor and lifetime prediction in on state 41 4-3 Scaling factor and lifetime prediction in off state 42 4-4 Scaling factor and lifetime prediction in subthreshold 43 4-5 Summary 44 Chapter 5 59 5-1 Conclusion 59 5-2 Future work 61 References 62

    [1] B. S. Doyle and K. R. Mistry, "Anomalous hot-carrier behavior for LDD P-Channel Transistors," Ieee Electron Device Letters, vol. 14, no. 11, pp. 536-538, Nov 1993.
    [2] Y. Shi, N. Feilchenfeld, R. Phelps, M. Levy, M. Knaipp, and R. Minixhofer, "Drift design impact on quasi-saturation & HCI for scalable N-LDMOS," in 2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs, 2011, pp. 215-218.
    [3] M. Zitouni et al., "A new lateral power MOSFET for smart power ICs: the "LUDMOS concept"," Microelectronics Journal, vol. 30, no. 6, pp. 551-561, Jun 1999.
    [4] W. F. Sun et al., "Hot-Carrier-Induced On-Resistance Degradation of n-Type Lateral DMOS Transistor With Shallow Trench Isolation for High-Side Application," Ieee Transactions on Device and Materials Reliability, vol. 15, no. 3, pp. 458-460, Sep 2015.
    [5] D. Varghese et al., "OFF-State degradation in drain-extended NMOS transistors: Interface damage and correlation to dielectric breakdown," Ieee Transactions on Electron Devices, vol. 54, no. 10, pp. 2669-2678, Oct 2007.
    [6] D. Varghese, A. Venugopal, S. Pan, and S. Krishnan, "Sub-threshold current based acceleration and modeling of OFF-state TDDB in drain extended NMOS and PMOS transistors," in 2013 IEEE International Reliability Physics Symposium (IRPS), 2013, pp. 5A.5.1-5A.5.4.
    [7] D. Varghese, M. Nandakumar, S. Tang, V. Reddy, and S. Krishnan, "Energy driven modeling of OFF-state and sub-threshold degradation in scaled NMOS transistors," in 2014 IEEE International Reliability Physics Symposium, 2014, pp. 4A.2.1-4A.2.4.
    [8] D. Varghese, G. Mathur, V. Reddy, J. Heater, and S. Krishnan, "Simulation and modeling of hot carrier degradation of cascoded NMOS transistors for power management applications," in 2012 IEEE International Reliability Physics Symposium (IRPS), 2012, pp. 3B.3.1-3B.3.4.
    [9] L. Dupont, S. Lefebvre, M. Bouaroudj, Z. Khatir, J. C. Faugieres, and F. Emorine, "Ageing Test Results of low voltage MOSFET Modules for electrical vehicles," in 2007 European Conference on Power Electronics and Applications, 2007, pp. 1-10.
    [10] C. Buttay, H. Morel, B. Allard, P. Lefranc, and O. Brevet, "Model requirements for simulation of low-voltage MOSFET in automotive applications," IEEE Transactions on Power Electronics, vol. 21, no. 3, pp. 613-624, 2006.
    [11] F. Chimento, G. Lazzaro, S. Musumeci, and A. Raciti, "Analysis and Comparison of Low-Voltage MOSFET Devices with Planar and Trench-gate Layouts," in 4th International Conference on Integrated Power Systems, 2006, pp. 1-6.
    [12] !!! INVALID CITATION !!! {}.
    [13] C. Kueing-Long, S. A. Saller, I. A. Groves, and D. B. Scott, "Reliability effects on MOS transistors due to hot-carrier injection," IEEE Transactions on Electron Devices, vol. 32, no. 2, pp. 386-393, 1985.
    [14] F. C. Hsu and S. Tam, "Relationship between MOSFET degradation and hot-electron-induced interface-state generation," IEEE Electron Device Letters, vol. 5, no. 2, pp. 50-52, 1984.
    [15] H. Chenming, C. T. Simon, H. Fu-Chieh, K. Ping-Keung, C. Tung-Yi, and K. W. Terrill, "Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement," IEEE Journal of Solid-State Circuits, vol. 20, no. 1, pp. 295-305, 1985.
    [16] Y. Toyoshima, H. Nihira, M. Wada, and K. Kanzaki, "Mechanism of hot electron induced degradation in LDD NMOS-FET," in 1984 International Electron Devices Meeting, 1984, vol. 30, pp. 786-789.
    [17] H. Katto, K. Okuyama, S. Meguro, R. Nagai, and S. Ikeda, "Hot carrier degradation modes and optimization of LDD MOSFETs," in 1984 International Electron Devices Meeting, 1984, vol. 30, pp. 774-777.
    [18] M. K. Orlowski and C. Werner, "Model for the electric fields in LDD MOSFETs. II. Field distribution on the drain side," IEEE Transactions on Electron Devices, vol. 36, no. 2, pp. 382-391, 1989.
    [19] A. Sadat, L. Yi, Y. Chuanzhao, and J. S. Yuan, "Analysis and modeling of LC oscillator reliability," IEEE Transactions on Device and Materials Reliability, vol. 5, no. 1, pp. 119-126, 2005.
    [20] F. C. Hsu and H. R. Grinolds, "Structure-enhanced MOSFET degradation due to hot-electron injection," IEEE Electron Device Letters, vol. 5, no. 3, pp. 71-74, 1984.
    [21] E. E. King, R. C. Lacoe, and J. Wang-Ratkovic, "The role of the spacer oxide in determining worst-case hot-carrier stress conditions for NMOS LDD devices," in 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059), 2000, pp. 83-92.
    [22] M. M. Lunenborg, H. C. d. Graaff, A. J. Mouthaan, and J. F. Verweij, "Anomalous NMOSFET Substrate Current Behavior at Accelerated Hot-Carrier Stress Conditions," in Solid State Device Research Conference, 1995. ESSDERC '95. Proceedings of the 25th European, 1995, pp. 813-816.
    [23] C. R. Yan et al., "Characteristics of Lateral Diffused Metal-Oxide-Semiconductor Transistors with Lightly Doped Drain Implantation through Gradual Screen Oxide," Japanese Journal of Applied Physics, vol. 52, no. 4, Apr 2013, Art. no. Unsp 04cc07.
    [24] S. Saha, C. S. Yeh, and B. Gadepally, "IMPACT IONIZATION RATE OF ELECTRONS FOR ACCURATE SIMULATION OF SUBSTRATE CURRENT IN SUBMICRON DEVICES," Solid-State Electronics, vol. 36, no. 10, pp. 1429-1432, Oct 1993.
    [25] W. Maes, K. Demeyer, and R. Vanoverstraeten, "IMPACT IONIZATION IN SILICON - A REVIEW AND UPDATE," Solid-State Electronics, vol. 33, no. 6, pp. 705-718, Jun 1990.
    [26] S. Reggiani et al., "TCAD Simulation of Hot-Carrier and Thermal Degradation in STI-LDMOS Transistors," Ieee Transactions on Electron Devices, vol. 60, no. 2, pp. 691-698, Feb 2013.
    [27] P. Heremans, R. Bellens, G. Groeseneken, and H. E. Maes, "THE GENERATION AND CHARACTERIZATION OF ELECTRON AND HOLE TRAPS CREATED BY HOLE INJECTION DURING LOW GATE VOLTAGE HOT-CARRIER STRESSING OF N-MOS TRANSISTORS - COMMENT," Ieee Transactions on Electron Devices, vol. 39, no. 2, pp. 458-&, Feb 1992.
    [28] G. B. Lee et al., "A Novel Technique for Curing Hot-CarrierInduced Damage by Utilizing the Forward Current of the PN-Junction in a MOSFET," Ieee Electron Device Letters, vol. 38, no. 8, pp. 1012-1014, Aug 2017.
    [29] R. Shing-Hwa, J. L. Pelloie, and F. Balestra, "Hot-carrier effects and reliable lifetime prediction in deep submicron N- and P-channel SOI MOSFETs," IEEE Transactions on Electron Devices, vol. 45, no. 11, pp. 2335-2342, 1998.
    [30] W. Waisum, A. Icel, and J. J. Liou, "A model for MOS failure prediction due to hot-carriers injection," in Proceedings 1996 IEEE Hong Kong Electron Devices Meeting, 1996, pp. 72-76.
    [31] R. Shing-Hwa, E. Rauly, J. L. Pelloie, and F. Balestra, "Hot-carrier effects and lifetime prediction in off-state operation of deep submicron SOI N-MOSFETs," IEEE Transactions on Electron Devices, vol. 45, no. 5, pp. 1140-1146, 1998.
    [32] T. D. Gilio and A. Bravaix, "Lifetime prediction of ultra-thin gate oxide PMOSFETs submitted to hot hole injections," in 2005 IEEE International Integrated Reliability Workshop, 2005, p. 5 pp.

    下載圖示
    2021-07-05公開
    QR CODE