隨著無線網路快速發展，資料安全的問題也日益受到重視，為了保護資料安全，在資料傳送之前加密是一般廣泛使用的方式。在過去的研究裡指出，舊有的資料加密演算法—DES (Data Encryption Standard) 已遭受質疑，無法提足夠的安全性，於是美國 NIST (National Institute of Standards and Technology)組織在2001年公開發表一個全新的加密演算法-- AES(Advanced Encryption Standard)，以取代舊有的加密演算法，目前已經有許多無線網路標準採用AES加密演算法做為其加密機制。
在本論文中，我們針對無線網路使用環境資源受限情況下，提出一個低成本、低功率的AES硬體架構。此架構可以有效的降低整體晶片面積與功率消耗，而資料處理量也足以應付無線網路的需求。我們是採用TSMC .13um的製程以及 Synopsys Astro 佈局後結果進行分析。根據我們提出來的方法電路僅需要12.4K個邏輯閘並且能達348.58Mbps的高速資料處理量；在10MHz操作頻率下，功率消耗只需要505.9μW。

With the rapid growth of wireless networks, the data security becomes an important issue. In order to protect data, a general approach is to encrypt the data before transmission. In the past, DES was the most popular encryption mechanism. However, it is found later that DES can not provide adequate security. On November 26, 2001, The U.S.A NIST (National Institute of Standards and Technology) announces a new encryption algorithm – AES to replace DES as the default encryption algorithm because of its strong encryption capability. Now, AES is adopted widely in most communication technologies, especially in the wireless networks which are peculiar vulnerable to eavesdropping.

In this thesis, we proposed a low-cost and low-power architecture for AES design for the resource-constrained wireless network. This architecture can reduce the chip area effectively and minimize the power consumption dramatically, while allowing the processing speed to meet the requirements of the wireless network. The netlist is generated by using TSMC .13 um CMOS processes and Synopsys’s Astro. The proposed AES design only demands 12.4K gate counts while achieving 348.58Mbps processing speed. The power consumption is 505.9μW at 10MHz operating frequency.

[1] National Bureau of Standards, “Data Encryption Standard”, U.S. Department of Conference, FIPS Pub. 46, Jan. 1977.
[2] National Institute of Standards and Technology (NIST). Advanced Encryption Standard AES. FIPS Pub. 197, Nov. 2001. Available at http://csrt.nist.gov/encryption/
aes/index.html
[3] IEEE Standard for Information technology – Telecommunications and information exchange between systems – Local and metropolitan area networks Specific requirements Part 15.3: Wireless Medium Access Control and Physical Layer Specifications for High Rae Wireless Personal Area Networks
[4] IEEE Standard for Information technology – Telecommunications and information exchange between systems – Local and metropolitan area networks Specific requirements Part 15.4: Wireless Medium Access Control and Physical Layer Specifications for Low-Rate Wireless Personal Area Networks
[5] IEEE Standard for Local and metropolitan area networks – part16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems.
[6] FIPS open test code – AESAVS (Advanced Encryption Standard Algorithm Validation Suite)
[7] T. Ichikawa, T. Kasuya, and M. Matsui, “Hardware Evaluation of the AES Finalists”, In the Proceeding 3rd AES Candidate Conference, printed by the National Institute of Standards and Technology Gaithersburg, MD, pp. 279-285, April 13-14, 2000.
[8] V. Rijmen. “Efficient implementation of the Rijndael S-box” Available at http:// www.esat.kuleuven.ac.be/~rijmen/rijndael/sbox.pdf, 2001
[9] A. Rudra, P. Dubey, C. Jutla, V.Kumar, J. Rao, P. Rohatgi. “Efficient Rijndael Encryption Implementation with Composite Field Arithmetic”, Proceedings of the 3rd International Workshop on Cryptographic Hardware and Embedded Systems (CHES), Vol. 2162 of Lecture Notes In Computer Science (LNCS), pp.171-184, 2001.
[10] A. Satoh, S. Morioka, K. Takeano, and S. Munetoh. “A compact Rijndael hardware architecture with S-box optimization”, Proceedings of the 7th International Conference on the Theory and Application of Cryptology and Information Security, LNCS vol. 2248, pp. 239-254, 2001.
[11] M. H. Lee “A Gbps AES Cipher”, Department of Computer Science National Tsing Hua University. 2001.
[12] J. Wolkerstorfer, E. Oswald, M. Lamberger. “An ASIC Implementation of the AES SBoxes” CT-RSA 2002, LNCS vol. 2271, pp. 67-78. , 2002.
[13] S. Morioka, A. Satoh, “An Optimized S-Box Circuit Architecture for Low Power AES Design”, CHES, LNCS vol. 2523, pp. 172-186, 2002.
[14] C. C. Lu, S. Y Tseng, ”Integration of AES (Advanced Encryption Standard) encrypter and decrypter, ” in Proceeding, Application-Specific Systems, Architecture and Processor, pp277-285, 2002.
[15] C.P. Su, T.F. Lin, C.T. Huang, and C.W. Wu. “A High-Throughput Low-Cost AES Processor”, IEEE communications Magazine, Dec. pp. 86-91, 2003
[16] S. Mangard, M. Aigner, and S. Dominikus, “A Highly Regular and Scalable AES Hardware Architecture,” IEEE Transaction on Computer, vol. 52, no. 4, pp. 483–91, Apr. 2003.
[17] I. Verbauwhede, P. Schaumont, and H. Kuo, “Design and Performance Testing of a 2.29-GB/s Rijndael Processor”, IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 569–72, Mar. 2003
[18] K. Chen. “Design and Implementation of Advanced Encryption Standard”, Institute of Electronics Engineering, National Taiwan University, 2003.
[19] M.C. Wu. “A Low-Cost Hardware Design and Implementation of AES Algorithm”, Institute of Communication engineering College of Electrical Engineering and Computer Science, National Chiao Tung University. 2003.
[20] S.C. Lu. “On the Design of AES Based on Dual Cipher and Composite Field”, Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C, 2003.
[21] H.C. Wang, C.H. Lin, A.Y. Wu. “Design and Implementation of cost-efficient AES Cryptographic Engine” Institute of Electronics Engineering, National Taiwan University, 2003.
[22] S.Y. Wu, S.C. Lu, C.S. Laih. “Design of AES Based on Dual Cipher and Composite Field”, CT-RSA, LNCS Vol. 2964, pp. 25-38, 2004.
[23] S. Chantarawong, P. Noo-intara, and S. Choomchuay. “An architecture for S-Box Computation in the AES”, IEEE International Conference on Electronics Pckaging, pp. 157-162, 2004.
[24] A. Hodjat, I. Verbauwhede, “Minimum Area Cost for a 30 to 70 Gbits/s AES Processor”, IEEE Computer Society Annual Symposium on CLSI Emerging Trends in CLSI System Design, 2004.
[25] N. Mentens, L. Batina, B. Preneel, I. Verbauwhede. “A Systematic Evaluation of Compact Hardware Implementations for the Rijndael S-Box”, 2005.
[26] J. Daemen and V. Rijmen, “The Design of Rijndael” AES – The Advanced Encryption Standard, Springer-Verlag, 2001.
[27] 賴溪松、韓亮、張真誠, “近代密碼學及其應用”, 松崗出版社, 2000年