隨著半導體工業持續發展，為了達到提升數位積體電路的速度、功能與降低製作成本要求下，元件尺寸微縮卻逐漸衍生諸多的短通道效應，造成元件特性劣化，因此，SOI基板逐漸受到重視。於符合超薄通道之需求，一般需要SOI基板之矽層厚度"≤ 25 nm" 且具高均勻度。然隨矽層厚度越薄製備愈形困難、成本越高。為改善此問題，本論文提出一種利用離子佈植技術來實現超薄通道之新穎場效電晶體，簡稱CTIFET (channel thinning by ion implantation)，藉由離子佈植技術精準地控制雜質深度、範圍與劑量，有效減少通道厚度同時保有平坦化的源極/通道/汲極結構，使FD-SOI製程不受SOI基板矽層厚度的限制，且可增加閘極對通道的控制能力與降低關閉狀態之漏電電流，有效改善元件短通道特性，提供一新穎超薄通道電晶體製備方法。此外，亦可將原先90 nm製程技術節點特性提升至28 nm製程技術節點特性，除具新穎性與進步性外，亦具應用價值。
本論文所使用之半導體元件模擬軟體為Sentaurus TCAD，其中元件所設定的供應電壓與等效氧化層厚度等參數參考國際半導體技術指標(International Technology Roadmap for Semiconductors, ITRS) 90 nm製程技術節點之預測為主，為使分析結果更接近實際狀況，本論文採用Sentaurus的SPROCESS軟體進行製程的模擬。
本研究首先針對CTIFET元件於離子佈植時所使用到的重要參數、不同摻雜型態以及佈植範圍作元件電特性分析。結果顯示在離子佈植技術下以晶圓無旋轉方式且採用能量9.5 keV、劑量8×1013cm-2、角度60度角以及氮氣環境(1050 oC、5 s)下的快速熱退火能夠獲得較佳的靜電特性。於適當的離子佈植控制下可使元件通道厚度薄化外，亦有助提升CTIFET的元件電特性。再者，於適當的離子佈植長度下，除可進一步優化元件之開關特性外，亦可大幅改善短通道效應以及降低串聯電阻。此外，我們亦與絕緣層上矽超薄通道場效電晶體及掘入式電晶體進行短通道特性的比較。結果顯示，不論在90 nm或是28 nm技術節點，本論文所提出CTIFET元件除製程簡易外亦具較佳的電特性。
最後，本研究也評估CTIFET應用於反相器及6T靜態隨機存取記憶體的表現。於反相器應用方面，模擬結果顯示元件面積尺寸對於其雜訊邊界有較大之影響，n/p-CTIFET的匹配程度對應用特性扮演極重要腳色。本元件n/p-CTIFET優異之電性對稱性及良好的閘極控制能力，使其雜訊邊界高達529 mV。於6T-SRAM方面，改變供應電壓或記憶體單元尺寸皆可優化其讀寫效能和提高穩定性，然而，此舉亦將改變電路之操作速度以及消耗功率。本元件n/p-CTIFET通道開關能力匹配性佳，因此其雜訊邊界無內縮現象，穩定性極佳，RSNM值與WSNM值分別為228 mV、461 mV。於元件結構參數選擇上，除需在讀寫間性能取捨外，亦必須考慮其於操作速度及消耗功率上之代價以取得最佳的平衡。
不論是於靜電特性或數位電路應用上，本論文所提出具新穎性、平面式之CTIFET元件均較傳統絕緣層上矽超薄通道場效電晶體及掘入式電晶體更優異之特性。本論文所提出CTIFET元件結構設計與電特性之模擬分析，具新穎性與進步性，可供半導體產業進行最適化製程之開發及更先進積體電路之應用參考。

In this study, a junctionless (JL) SOI FET with channel thinning by ion implantation (CTI), called CTIFET is proposed for the first time and its application to inverter and 6T-SRAM are presented. Simulation results based on Sentaurus TCAD are presented and discussed. It reveals that the proposed device which has channel thickness reduced from 25 nm to below 10 nm. CTIFET shows the lowest values in Ioff, SS and DIBL. Similar improvement in device performance is also obtained from p channel devices. As compared to ultra-thin body FET (UTBFET) and recessed-channel FET (RCFET) with a 10-nm-thick silicon channel, could significantly increase Ion, suppress Ioff, and reduce SS by about 3.4%, 81.2%, and 2.9%, respectively.
In addition, the CMOS inverter based on CTIFET. A noise margin as high as 529 mV is obtained. And 6T-SRAM shows an SNM at Vdd=1.2 V as high as 228 and 461 mV during read and write operation, respectively. The inverter and 6T-SRAM performances are attributed to the considerable harvest of gate control originating from channel thinning through ion implantation.

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