本篇論文主要目的是對n型通道橫向擴散金氧半場效應電晶體之熱載子可靠度，做一個初步的研究。藉由與業界合作的關係，取得0.5m製程技術的元件，探討高壓元件與傳統低壓元件熱載子效應以及其可靠度的不同。
　　隨著時代的演進，微電子晶片輕、薄、短、小的訴求與日俱增。由於製程技術的不斷推陳出新，邏輯電路晶片的密度正以驚人的速度逐漸向上攀升。然而有一部分的需求，則希望可以將高電壓的元件也整合進入一般晶片內，如此一來，晶片組的面積則可以獲得更進一步的縮減，LDMOS於是應運而生。傳統的MOSFET熱載子可靠度的探討，已經具有相當多的文獻以及資料可以探討，整個可靠度模型的建置也已經趨於成熟。然而，對於這種高壓元件的熱載子可靠度，則較少學者加以探討，職事是故，本篇論文將對於此種高壓元件做一個初步熱載子效應的研究與探討。
　　本文架構是由傳統低壓MOSFET的可靠度出發，藉由這些相當成熟的模型為基礎，進一步分析高壓元件的行為。本篇論文可以分為五個章節：第一章對於LDMOS電晶體以及熱載子效應的基本資料做一個介紹。第二章則是介紹低壓元件的熱載子可靠度是如何加以建立。從如何量化熱載子效應的嚴重程度，stress方法論的介紹，到最後進行加速測試的方式都有簡單的介紹。
　　第三章則是探討在高壓元件中有哪些和低壓元件不同的行為。經過實驗發現，在低壓元件所沒有的克爾克效應(Kirk Effect)會在此種LDMOS電晶體當中浮現，這導致過去認為的退化程度與基板電流(substrate current)大小呈現正比關係在這個元件中遭到打破。此外，此種LDMOS電晶體遭到stress後，元件退化的速度會在一定的時間之後飽和，這也和過去非輕摻雜汲極(non-LDD)MOSFET所觀察到的退化狀況有很大的出入。另外，最令人訝異的是，此種LDMOS電晶體在經過靜置後，元件退化會下降(relaxation)，這個現象意味著元件特性會因為「休息」而「恢復」。如此一來，對於過去所有熱載子可靠度的方法都必須經過一番修正後，才能再度使用。這些現象在論文中都有相當詳細的探討。
　　第四章則是針對第三章所發現異於低壓MOSFET的現象所找到的元件生命期模型(lifetime model)做一個探討，此外也由於這麼多和低壓元件不同的退化行為，所以我們也提出了一些關於高壓元件熱載子可靠度方法論的一些修正。第五章則是做一個總結，並且提出這篇論文一些尚未完成的方向以便後來繼續做深入的探討以及研究。

　　The hot carrier reliability of conventional MOSFETs is established completely by other authors. However, fewer authors study the hot carrier reliability of LDMOS transistors. The thesis will study the hot carrier reliability of n-channel LDMOS transistors.
　　I use the method based on the conventional MOSFETs to investigate LDMOS transistors. I discover that three main differences between conventional MOSFETs and LDMOS transistors: 1. Kirk effect, 2. degradation saturation, 3. relaxation phenomenon. Because of the difference, the Isub vs. lifetime will not be the same as the conventional MOSFETs.

[1]S. A. Abbas and R.C. Dockerty, “N-Channel IGFET Design Limitations due to Hot-Electron Trapping,” IEDM Tech. Digest 35. p.122 (1975)
[2]T. H. Ning, C. M. Osburn, and H. N. Yu, “Effect of Electron Trapping in IGFET Characteristics,” J. Electron. Mat. 6, p.93 (1977).
[3]C.Y. Chang, S.M. Sze, “ULSI Devices”, Wiley (2000).
[4]Wolf, “The Silicon Processing for the VLSI Era” Vol.3, Lattice (1995).
[5]T.Y. Chan, P.K. Ko, and C. Hu, “A Simple Method to Characterize Substrate Current in MOSFETs,” IEEE Electron Dev. Letts., EDL-5, p.150 (1984).
[6]Eiji Takeda, Cary Y. Yang, Akemi Miura-Hamada, “Hot-Carrier Effects in MOS Devices”, Academic Press, (1995).
[7] F.H. Hsu and K.Y. Chiu, “A Comparative Study of Tunneling, Substrate Hot-Electron, and Channel Hot-Electron Injection Induced Degradation in Thin-Gate MOSFETs,” Tech. Dig. IEDM, p.234 (1984)
[8]P. Yang and S. Aur, ”Modeling of Device Lifetime due to Hot Carrier Effects,” Proc. of 1985 Internat. Symp. On VLSI Tech., p. 227 (1985)
[9]C. Hu, “Hot-Carrier Effects,” Chap. 3, in Advanced MOS Device Physics, N.G. Einspruch and G. Gildenblat, Eds., Vol. 18, VLSI Electronics Microstructure Science, Academic Press, San Diego, CA, p.119 (1989)
[10] T.Y. Chan, C.I. Chiang, and H. Gaw, “New Insight into Hot-Electron-Induced Degradation of n-MOSFETs,” Tech. Dig. IEDM, p.196 (1988)
[11]J.Y. Choi, P.K. Ko, and C. Hu, “Hot-Carrier-Induced MOSFET Degradation: AC versus DC stressing,” Dig. Tech. Papers Symp. VLSI Tech , p. 45 (1987)
[12]E. Takeda and N. Suzuki, “An Empirical Model for Device Degradation due to Hot Carrier Injection,” IEEE trans. Electron Dev. Letts., EDL-4. p. 111, (1983).
[13]F.-C. Hsu and K.Y. Chiu, “Hot-Electron Substrate-Current Generation During Switching Transient,” IEEE Trans. Electron Dev., ED-32, p. 375 (1985).
[14]T.K. Horiuchi, H. Mikoshiba, K. Nakamura, and F. Hamano, “A Simple Method to Evaluate Device Lifetime Due to Hot-Carrier Effect Under Dynamic Stress,” IEEE Trans. Electron Dev. Letts., EDL-7, p.377, (1986)
[15]K.R. Hoffmann, W. Weber, C. Werner, and G. Dorda, “Hot-Carrier Degradation Mechanism in N-MOSFETs,” Tech. Dig. IEDM, p. 104 (1984)
[16]W. Weber, C. Werner and A. Schwerin, “Lifetimes and Substrate Currents in Static and Dynamic Hot-Carrier Degradation,” Tech. Dig. IEDM, p. 390 (1986)
[17]K.L. Chen, S. Saller, and R. Shah, “The Case of AC Stress in the Hot-Carrier Effect,” IEEE Trans. Electron Dev., ED-33, March 1986, p. 424 (1986)
[18]B.S. Doyle et al., “Dynamic Channel Hot-Carrier Degradation of MOS Transistors by Enhanced Electron-Hole Injection into the Oxide,” EDL-8, May 1987, p. 237 (1987)
[19]J.Y. Choi, P.K. Ko, and C. Hu, “Hot-carrier induced MODFET degradation under AC stress” IEEE trans. Electron Dev. Letts., EDL-8, p. 333 (1987)
[20]R. Bellens et al., “Analysis of mechanisms for the Enhanced Degradation During AC Hot Carrier Stress of MOSFETs,”Tech. Dig. IEDM, p. 212 (1988)
[21]W. Weber et al., “Dynamic Degradation in MOSFETs – Part II: Application in the Circuit Environment,” ED-38, p. 1859 (1991)
[22]K.R. Mistry et al., “Circuit Design Guidelines for n-Channel MOSFET Hot Carrier Robustness,” IEEE Trans. Electron Dev., ED-40, July 1993, p. 1284 (1993)
[23] S.M. Sze, “Physics of Semiconductor Devices“, Wiley (1981).
[24] Ben G. Streetman, Sanjay Banerjee, “Solid state electronic devices”, 5th ed, Prentice Hall (2000)
[25] Yuan Taur, Tak h. Ning, “Fundamentals of modern VLSI devices”, Cambridge (1998)
[26] A.W. Ludikhuize, “Kirk effect limitations in high voltage IC’s”, IEEE, p.249 (1994)
[27]A. W. Ludikhuize, “A Review of RESURF Technology”, ISPSD, p.11 (2000)
[28]S.K. Lee, C.J. Kim, J.H. Kim, Y.C. Choi, H.S. Kang and C.S. Song, “Optimization of Safe-Operating Area Using Two Peaks of Body-Current in Submicron LDMOS Transistors”, ISPSD (2001)
[29]V.H. Chan, James E. Chung, “Two-Stage Hot-Carrier Degradation and its impact on Submicron LDD NMOSFET Lifetime Prediction”, IEDM, p.515 (1993)
[30]A. Raychauduri, M.J. Deen, W.S. Kwan, and M.I.H. King, “Features and Mechanisms of the Saturating Hot-Carrier Degradation in LDD NMOSFET’s”, IEEE TED, p.1114 (1996)
[31]B. S. Doyle et al., “Relaxation Effects in NMOS Transistors After Hot-Carrier Stressing”, IEEE-EDL, p.234 (1987)