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研究生: 陳虹霖
Chen, Hong-Lin
論文名稱: 以非平衡格林函數模擬低溫下具源極至汲極穿隧之奈米尺寸金氧半場效電晶體
Source-to-Drain Tunneling of Nanoscale MOSFETs at Cryogenic Temperatures by NEGF Simulation
指導教授: 高國興
Kao, Kuo-Hsing
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 奈米積體電路工程碩士博士學位學程
MS Degree/Ph.D. Program on Nano-Integrated-Circuit Engineering
論文出版年: 2020
畢業學年度: 108
語文別: 英文
論文頁數: 33
中文關鍵詞: 非平衡格林函數量子傳輸雙閘極金氧半場效電晶體不完全解離效應
外文關鍵詞: non-equilibrium Green’s function (NEGF), quantum transport, double-gate MOSFETs, incomplete ionization
相關次數: 點閱:142下載:19
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  • 隨著半導體技術的日新月異,元件尺寸微縮技術在其中扮演重要的角色,持續發展至今已進入奈米等級的世代,也因此衍伸出逼近半導體元件物理極限需面對的各種挑戰。本論文中使用的 nanoMOS4.0 模擬主要以非平衡格林函數(NEGF)解薛丁格方程式,分析在奈米尺寸雙閘極金氧半場效電晶體元件中,電子呈現的量子傳輸行為,進一步與波松方程式相互迭代產生最終收斂,再求得其電子密度和電流等元件特性。
    近幾年來由於量子運算的發展潛能, 並因應現今強大運算的需求與商業可行性應用於量子電腦中的 量子運算控制晶片如何透過系統化擴展到量子實用性所需的數千個量子位元 成為一大挑戰,晶片中的極低溫互補式金氧半場效電晶體 (Cryo-CMOS)相關技術研究也跟著蓬勃發展 。 本論文在計算量子傳輸的基礎下,加入元件中的摻雜於溫度下降至 4K 時,可能遇到不完全解離的效應,以及於製程中由源極與汲極產生的橫向摻雜擴散,探討隨著縮減通道長度對元件特性的影響。
    最後由結果可得知不只溫度下降,縮減通道長度及橫向摻雜擴散皆能加劇不完 全解離效應對元件特性的衝擊,並且了解通道長度縮短時,在源極與汲極間出現的直接穿隧電流,其增加將改變次臨界電流的組成,進而抑制次臨界擺福隨溫度下降達到飽和狀態。

    As the progress in the semiconductor industry, downsizing the critical dimensions of devices to nanascale has played a significant role until now. Thus, it’s getting so closer to the fundamental limits of semiconductor physics that there are all kinds of challenges for us to conquer. In this thesis, the nanoMOS4.0 simulator applies the non-equilibrium Green’s function (NEGF) to solving the Schrödinger equation for the quantum transport of electrons in a nanoscale double-gate MOSFET. By the self-consistently iteration of the Schrödinger equation and the Poisson equation, we can thus obtain the electron density and current, etc.
    Because of the potential of quantum computing for the powerful computing ability and commercial feasibility, the quantum computer technology has rapidly developed in recent years. However, how to systematically realize the quantum practicality by the controlling chips has become a big challenge. Applied to the fabrication of the chips for quantum operation controlling, Cryo-CMOS technology thus flourishes. On the basis of calculating the quantum transport, the incomplete ionization at temperatures lowering to 4 K is taken into account in the thesis. Additionally, the lateral doping diffusion from the process is also considered to investigate their influences on the device characteristics with the channel length decreasing.
    It’s shown that reducing the channel length and the lateral doping diffusion extending can let the effect of incomplete ionization on the transfer characteristics more noticeable besides low temperatures. Moreover, the direct tunneling current crossing through the barrier between the source and drain causes the transformation in the subthreshold region and even suppresses subthreshold swing lowering at low temperatures into the saturation.

    摘要....................................................I Abstract...............................................II 誌謝..................................................III Contents...............................................IV Table captions..........................................V Figure captions........................................VI Chapter I Introduction..................................1 1.1 Device Scaling and Short Channel Effects............1 1.2 MOSFET Device Characteristics.......................3 1.3 Semi-Classical Model and Material Parameters at Cryogenic Temperature...................................5 1.4 The Research objective and the dissertation outline .......................................................10 Chapter II Models for the Simulation...................11 2.1 Incomplete Ionization and Dopant Ionization Energy Variation..............................................11 2.2 The Non-Equilibrium Green’s Function (NEGF) Formalism .......................................................15 Chapter III Electrical Characteristics of MOSFETs at Cryogenic Temperatures.................................21 3.1 Device Structure...................................21 3.2 Results and Discussion.............................22 Chapter IV Conclusion and Future Work..................31 4.1 Conclusion.........................................31 4.2 Future Work........................................31 References.............................................32

    References in chapter 1
    [1]https://www.icinsights.com/news/bulletins/Transistor-Count-Trends-Continue-To Track-With-Moores-Law/
    [2] Peter M. Zeitzoff and Howard R. Huff, ‘‘MOSFET Scaling Trends, Challenges, and Key Associated Metrology Issues Through the End of the Roadmap”, AIP Conference Proceedings, 788, pp. 203-213, September 2005.
    [3] http://userweb.eng.gla.ac.uk/fikru.adamu-lema/Chapter_02.pdf
    [4] Leland Chang and Chenming Hu, ‘‘MOSFET scaling into the 10 nm regime”, Superlattices and Microstructures, Vol.28, No. 5–6, pp. 351-355, 2000.
    [5] J. Wang and M. Lundstrom, ‘‘Does source-to-drain tunneling limit the ultimate scaling of MOSFETs?’’, IEDM, pp. 707–710, December 2002.
    [6] S. M. Sze, K. K. Ng, Physics of Semiconductor Devices, Hoboken, NJ, USA: Wiley, 2006.
    [7] V. Ganni and J.E. Fesmire, ‘‘Cryogenics for superconductors: Refrigeration, delivery, and preservation of the cold”, AIP Conference Proceedings, 1434, June 2012.
    [8] F. Jazaeri, A. Beckers et al., ‘‘A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics”, 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems", pp. 15-25, 2019.
    [9] Y. P. Varshni, “Temperature dependence of the energy gap in semiconductors”, Physica, vol. 34, no. 1, pp. 149–154, 1967.
    [10] N. Dao et al., “An enhanced MOSFET threshold voltage model for the 6–300 K temperature range”, Microelectronics Reliability, 69, pp. 36–39, 2017.
    [11] Arnout Beckers et al., “Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures”, Solid State Electronics, 159, pp. 106–115, 2019.
    [12] Vinod Kumar Khanna, “Extreme-temperature and Harsh-environment Electronics: Physics, Technology and Applications”, IOP Publishing, 2017.
    References in chapter 2
    [1] S. M. Sze, K. K. Ng, Physics of Semiconductor Devices, Hoboken, NJ, USA: Wiley, 2006.
    [2] P. P. Altermatt, A. Schenk, and G. Heiser, “A simulation model for the density of states and for incomplete ionization in crystalline silicon—Part I: Establishing the model in Si:P”, J. Appl. Phys., vol. 100, no. 11, pp. 113714, Dec 2006.
    [3] T. F. Lee and T. C. McGill, “Variation of impurity−to−band activation energies with impurity density”, J. Appl. Phys., 46, pp. 373-380, 1975.
    [4] Sentaurus™ Device User Guide, Synopsys, December 2019.
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    [5] M. R. Shaheed and C. M. Maziar, “A physically based model for carrier freeze-out in Si- and SiGe-base bipolar transistors suitable for implementation in device simulators,” BICMOS Circuits Technol. Meeting, pp. 191–194, 1994.
    [6] G. L. Pearson and J. Bardeen, “Electrical properties of pure silicon and silicon alloys containing boron and phosphorus,” Phys. Rev., vol. 75, no. 5, pp. 865–883, Mar. 1949.
    [7] P. P. Altermatt, A. Schenk, B. Schmithusen, and G. Heiser, “A simulation model for the density of states and for incomplete ionization in crystalline silicon—Part II: Investigation of Si:As and Si:B and usage in device simulation,” J. Appl. Phys., vol. 100, no. 11, pp. 113715, Dec. 2006.
    [8] Takahisa Tanaka et al., “Deionization of Dopants in Silicon Nanofilms Even with Donor Concentration of Greater than 1019 cm−3 ”, Nano Lett., 16, pp. 1143–1149, January 2016.
    [9] G. M. Guichar, et al., “Influence of Phonons on the Impurity Photoconductivity Spectrum of Phosphorus-Doped Silicon”, Phys. Rev., 5, 1972.
    [10] S. Toyotomi, “Far-Infrared Impurity Absorption in Highly Doped n-Type Silicon”, J. Phys. Soc. Jpn., 38, 1975.
    [11] W. Scott and C. E. Jones, “Infrared spectra of new acceptor levels in boron‐doped and gallium‐doped silicon”, J. Appl. Phys., 50, 1979.
    [12] M. Capizzi, et al., “Observation of the Approach to a Polarization Catastrophe”, Phys.Rev. Lett. 44, pp. 1019, 1980.
    [13] L. Stockmeier, “Heavily n-type doped silicon and the dislocation formation during its growth by the Czochralski method,” Fraunhofer Verlag, 2018.
    [14] Z. Ren, R. Venugopal, S. Goasguen, S. Datta and M. S. Lundstrom, “nanoMOS 2.5: A two-dimensional simulator for quantum transport in double-gate MOSFETs”, IEEE Transactions on Electron Devices, vol. 50, no. 9, pp. 1914-1925, Sept. 2003.
    [15] Z. Ren, Nanoscale MOSFETs: Physics, Simulation and Design, PhD Thesis, 2001
    [16] S. Datta, Quantum Transport: Atom to Transistor, CAMBRIDGE, 2005.
    [17] S. Datta, “Nanoscale Device Modeling: The Green's Function Method”, Superlattice. Microst., 28, pp. 253-278, 2000.
    [18] S. Datta, “The non-equilibrium Green's function (NEGF) formalism: An elementary introduction”, Digest. International Electron Devices Meeting, pp. 703-706, 2002.

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