在本論文中，我們針對不同佈局參數的高壓金氧半場效電晶體元件的特性以及熱載子可靠度進行深入討論並解釋物理機制。重要的佈局參數分別為L、Lgd及Ovl。分別對應到閘極長度、飄移區的長度與閘極邊緣到薄氧化層之間的長度。
在本論文中，首先會先簡單介紹目前高壓元件在業界的應用，並闡明崩潰機制與熱載子效應的基本原理。接著介紹在本論文中所用到的元件結構及基本電性的量測。為了更深入了解元件內部的物理機制，將使用電腦輔助設計(TCAD)來進行模擬分析。
第二部分則會介紹傳統接面與漸進接面結構，並敘述其製程上的差異，之後藉由基本電性的量測，包含線性區電流、飽和區電流、截止態崩潰電壓和基板電流，並觀察不同佈局參數對元件特性的影響。並預期L或Lgd的減少會增強線性區電流和飽和區電流。也確立了一些量測設定與參數萃取的條件。
第三部分則是討論元件的截止態崩潰電壓數據。漸進接面有較高的崩潰電壓，相較於傳統接面的結構，此現象在更大尺寸的元件中更明顯，反而在更小Lgd參數裡越不明顯。隨著介面缺陷的增加，會讓間隙物底部附近的碰撞游離分佈會發生變化，使得碰撞游離強度更小，且其位置也更遠離矽與二氧化矽界面處，並導致了退化飽和的現象。我們利用TCAD去觀察崩潰機制和解釋崩潰電壓改變的現象，藉由電流流線、電場強度和碰撞游離分布去分析比較，此外還有觀察到當元件處於崩潰電壓時，其空乏區寬度會有所不同。
第四部分則是佈局參數對於元件的熱載子可靠度與熱載子生命週期的影響。我們先表明加速測試的量測設定，再分析量測的數據並計算出其生命週期，並做出元件生命週期斜率圖。配合電腦輔助設計模擬，總結出熱載子退化的相關機制與現象。結果顯示傳統接面與漸進接面的退化程度沒有太大的差異，其元件生命週期也相似。

In this study, we explain the physical mechanism and discuss the characteristics and hot carrier reliability of n-type high-voltage MOSFET devices with different layout parameters. The critical layout parameters include L, Lgd, and Ovl, corresponding to the length of the gate, the length of the drift region, and the length from the gate edge to the thin oxide thickness.
In this study, first, we will briefly list the applications of high-voltage devices in the semiconductor industry, and introduce basic principles of breakdown mechanism and hot carrier effect. Then we illustrate the device structure and basic electrical measurement used in our study. In order to get a better understanding of the interior physical mechanism of devices, technology computer-aided design (TCAD) will be used for simulation analysis.
The second part will introduce the traditional junction and the gradual junction structure, and describe their differences in manufacturing process. After that, we observe the influence of different layout parameters on devices through basic electrical characteristic measurement, including the linear region current, the saturation region current, the off-state breakdown voltage and the substrate current. It is also expected that the reduction of L or Lgd will increase the current in the linear region and the saturation region. Some conditions for measuring settings and parameter extraction are also established.
The third part is the off-state breakdown voltage data of all devices. Devices of gradual junction own a higher breakdown voltage compared with the traditional junction, this phenomenon is more obvious in bigger dimension device, but less obvious in smaller Lgd parameter. With the increase of interface states, the distribution of impact-ionization near bottom of the spacer will change, making the magnitude of impact-ionization smaller and move away from the silicon/silicon dioxide interface, eventually leading to saturating degradation. We explain the phenomenon of changes in breakdown voltage by means of analyzing the current flowline, magnitude of electric field, and distribution of impact-ionization.
The fourth part is the influence of various layout parameters on the hot carrier reliability and lifetime. We first show the measuring setting of the accelerated test, then analyze the measured data and calculate its lifetime, finally making a plot of device lifetime. At last, the related mechanisms and phenomena of hot carrier degradation are summarized.

[1] Bianchi, R. A., et al. "High voltage devices integration into advanced CMOS technologies." 2008 International Electron Devices Meeting. IEEE, 2008.
[2] Meyer, W. G., et al. "Integrable high voltage CMOS: Devices, process application." 1985 International Electron Devices Meeting. IEEE, 1985.
[3] G. M. Dolny, O. H. Schade, B. Goldsmith and L. A. Goodman, "Enhanced CMOS for analog-digital power IC applications", IEEE Trans. Electron Devices, vol. ED-33, pp. 1985-1991, 1986.
[4] Wessels, Piet, et al. "Advanced BCD technology for automotive, audio and power applications." Solid-state electronics 51.2 (2007): 195-211.
[5] Chen, J. F., Chen, S. Y., Wu, K. M., Shih, J. R., & Wu, K. (2009). "Convergence of hot-carrier-induced saturation region drain current and on-resistance degradation in drain extended MOS transistors. " IEEE transactions on electron devices, 56(11), 2843-2847.
[6] P. Moens and G. V. den Bosch, "Characterization of total safe operating area of lateral DMOS transistors ", IEEE Trans. Device Mater. Rel., vol. 6, no. 3, pp. 349–357, Sep. 2006.
[7] J. A. Appels and H. M. J. Vaes, "High voltage thin layer devices (RESURF devices)," in IEDM Tech. Dig., Dec. 1979, pp. 238–241, doi: 10.1109/IEDM.1979.189589.
[8] T.-Y. Huang et al., "A novel 80 V HS-DMOS with gradual-RESURF profile to reduce Ron_sp for high-side operation, " in Proc. Int. Symp. Power Semicond. Device ICs (ISPSD), 2017, pp. 299–302.
[9] Chin-Rung Yan et al 2013 Jpn. J. Appl. Phys. 52 "Characteristics of Lateral Diffused Metal–Oxide–Semiconductor Transistors with Lightly Doped Drain Implantation through Gradual Screen Oxide."
[10] Shi, Yun, et al. "Drift design impact on quasi-saturation & HCI for scalable N-LDMOS." 2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs. IEEE, 2011.
[11] R. Stengl and U. Gösele, "Variation of lateral doping—A new concept to avoid high voltage breakdown of planar junctions, " in IEDM Tech. Dig., Washington, DC, USA, Dec. 1985, pp. 154–157, doi: 10.1109/ IEDM.1985.190917.
[12] B. Duan, Y. Huang, B. Zhang, and Z. Li, "Experiment results of REBULF LDMOS and analysis of a partial n+-floating structure, " J. Semicond., vol. 28, no. 8, pp. 1262–1266, 2007, doi: 0253-4177 (2007)08-1262-05.
[13] Chen, Jone F., et al. "On-resistance degradation induced by hot-carrier injection in LDMOS transistors with STI in the drift region." IEEE Electron Device Letters 29.9 (2008): 1071-1073.
[14] W. F. Sun et al., "Hot-carrier-induced on-resistance degradation of n-type lateral DMOS transistor with shallow trench isolation for high side application, " IEEE Trans. Device Mater. Rel., vol. 15, no. 3, pp. 458–460, Sep. 2015.
[15] Chen, Jone F., et al. "Drift region doping effects on characteristics and reliability of high-voltage n-type metal–oxide–semiconductor transistors." Japanese Journal of Applied Physics 55.1S (2015): 01AD03.
[16] Shi, Y., N. Feilchenfeld, R. Phelps, M. Levy, M. Knaipp, and R. Minixhofer (2011), "Drift Design Impact on Quasi-Saturation & HCI for Scalable N-LDMOS", IEEE International Symposium on Power Semiconductor Devices & IC's, San Diego, May, pp.215~218
[17] "An analytic three-terminal band-to-band tunneling model on GIDL in MOSFET" Jul 2001 IEEE Transactions on Electron Devices. IEEE, 2001.
[18] J. F. Chen et al., "Off-state avalanche-breakdown-induced on-resistance degradation in lateral DMOS transistors, " IEEE Trans. Electron Devices, vol. 28, no. 11, pp. 1033–1035, Nov. 2007.
[19] W. Feng, T. Y. Chan and C. Hu, "MOSFET drain breakdown voltage", IEEE Electron Device Lett., vol. EDL-7, no. 7, pp. 449-450, July 1986.
[20] T. Y. Chan, J. Chen, P. K. Ko and C. Hu, "The impact of gate-induced drain leakage current on MOSFET scaling", IEDM Tech. Dig., pp. 718-721, 1987-Dec.
[21] K. Kurimoto, Y. Odake, S. Odanaka, "Drain leakage current characteristics due to the band-to-band tunneling in LDD MOS devices", Electron Devices Meeting 1989. IEDM '89. Technical Digest. International, pp. 621-624, 1989.
[22] Chen, Ja-Hao, Shyh-Chyi Wong, and Yeong-Her Wang. "An analytic three-terminal band-to-band tunneling model on GIDL in MOSFET." IEEE Transactions on Electron Devices 48.7 (2001): 1400-1405.
[23] C. Chang, S. Haddad, B. Swaminathan, J. Lien, "Drain-avalanche and hole-trapping induced gate leakage in thin-oxide MOS devices", Electron Device Letters IEEE, vol. 9, no. 11, pp. 588-590, 1988.
[24] Siyang, Liu et al. "A Review on Hot-Carrier-Induced Degradation of Lateral DMOS Transistor." 2017 IEEE Transactions on Device and Materials Reliability. IEEE, 2017.
[25] Tsai, Yen-Lin, et al. "Investigation of characteristics and hot-carrier reliability of high-voltage MOS transistors with various doping concentrations in the drift region." Semiconductor Science and Technology 33.12 (2018): 125019.
[26] S.-Y. Chen et al., "Anomalous hot-carrier-induced increase in saturation region drain current in n-type lateral diffused metal-oxide semiconductor transistors, " IEEE Trans. Electron Devices, vol. 55, no. 5, pp. 1137–1142, May 2008.
[27] V. Vescoli et al., "Hot-carrier reliability in high-voltage lateral double diffused MOS transistors, " IET Circuits Devices Syst., vol. 2, no. 3, pp. 347–353, Jun. 2008.
[28] Hu, Chenming. Modern semiconductor devices for integrated circuits. Vol. 2. Upper Saddle River, New Jersey: Prentice Hall, 2010.
[29] Wolf, Stanley. "Silicon Processing for the VLSI era, Vol. 3: The submicron MOSFET." (1994).
[30] E. Riedlberger, C. Jungemann, A. Spitzer, M. Stecher, and W. Gustin, "Comprehensive analysis of the degradation of a lateral DMOS due to hot carrier stress, " in Proc. IEEE Int. Integr. Rel. Workshop Final Rep. (IIRW), 2009, pp. 77–81.
[31] P. Moens, F. Bauwens, M. Nelson, and M. Tack, "Electron trapping and interface trap generation in drain extended pMOS transistors, " in Proc. IEEE Int. Rel. Phys. Symp. (IRPS), San Jose, CA, USA, 2005, pp. 555–559.
[32] G. T. Sasse, J. A. M. Claes, and B. Vries, "An LDMOS hot carrier model for circuit reliability simulation, " in Proc. Int. Rel. Phys. Symp. (IRPS), 2014, pp. 5D-5.1–5D-5.6.
[33] Moens, Peter, et al. "Hot hole degradation effects in lateral nDMOS transistors." IEEE Transactions on Electron Devices 51.10 (2004): 1704-1710.
[34] Hu, Chenming, et al. "Hot-electron-induced MOSFET degradation-model, monitor, and improvement." IEEE Journal of Solid-State Circuits 20.1 (1985): 295-305.
[35] Chan, T. Y., P. K. Ko, and C. Hu. "A simple method to characterize substrate current in MOSFET's." IEEE Electron Device Letters 5.12 (1984): 505-507.
[36] J. F. Chen et al., "Mechanism and lifetime prediction method for hot-carrier-induced degradation in lateral diffused metal-oxide semiconductor transistors, " Appl. Phys. Lett., vol. 92, no. 24, 2008, Art. no. 243501.
[37] P. Moens and G. V. den Bosch, "Reliability assessment of integrated power transistors: Lateral DMOS versus vertical DMOS, " Microelectron. Rel., vol. 48, nos. 8–9, pp. 1300–1305, 2008.
[38] Silvaco, Int. "ATLAS user’s manual." Santa Clara, CA, Ver 5 (2011).
[39] Silvaco "Atlas User’s Manual" Silvaco, Inc. 4701 Patrick Henry Drive, Bldg. 2 Santa Clara, CA 95054,2012
[40] Silvaco "Athena User’s Manual" Silvaco, Inc. 4701 Patrick Henry Drive, Bldg. 2 Santa Clara, CA 95054,2013
[41] Silvaco "Guide to using TCAD with examples" 4701 Patrick Henry Drive, Bldg. 2 Santa Clara, CA 95054,2009
[42] Shvetsov-Shilovskiy, I. I., et al. "Measurement system for test memory cells based on keysight B1500A semiconductor device analyzer running LabVIEW software." 2017 International Siberian Conference on Control and Communications (SIBCON). IEEE, 2017.
[43] C.-L. Chu, C.-M. Hu, J. Gong, C.-F. Huang, C.-L. Tsai, F.-Y. Chen, R.-H. Liou, H.-C. Tuan, "Investigation of voltage-dependent drift region resistance on high-voltage drain-extended MOSFETs'' I-V characteristics", Electronics Letters, vol. 48, pp. 110, 2012.
[44] Jone F. Chen et al 2016 Jpn. J. Appl. Phys. 55 "Analysis of high-voltage metal–oxide–semiconductor transistors with gradual junction in the drift region."
[45] Chan, T. Y., P. K. Ko, and C. Hu. "A simple method to characterize substrate current in MOSFET's." IEEE Electron Device Letters 5.12 (1984): 505-507.
[46] Y. Nissan-Cohen, G. A. Franz and R. F. Kwasnick, "Measurement and analysis of hot-carrier-stress effect on NMOSFET's using substrate current characterization", IEEE Electron Device Lett., vol. EDL-7, pp. 451, 1986.
[47] C.-L. Chu, C.-M. Hu, J. Gong, C.-F. Huang, C.-L. Tsai, F.-Y. Chen, R.-H. Liou, H.-C. Tuan, "Investigation of voltage-dependent drift region resistance on high-voltage drain-extended MOSFETs'' I-V characteristics", Electronics Letters, vol. 48, pp. 110, 2012.
[48] H. Sasaki, H. M. Saitoh and K. Hashimoto, "Hot carrier induced drain leakage current in n-channel MOSFETs", EDM Tech. Dig., pp. 726, 1987.
[49] T. Grasser, H. Kosina, C. Heitzinger and S. Selberherr, "Accurate impact ionization model which accounts for hot and cold carrier populations", Appl. Phys. Lett., vol. 80, no. 4, pp. 613-615, 2002.
[50] J. M. Park, M. Knaipp, H. Enichlmair, R. Minixhofer, S. Yun, N. Feilchenfeld, "Hot-Carrier Behaviour and Ron-BV Trade-off Optimization for p-channel LDMOS Transistors in a 180 nm HVCMOS Technology, " Power Semiconductor Devices & IC's (ISPSD), Belgium, 2012, pp.189-192.
[51] A. Tallarico et al., "Investigation of the hot carrier degradation in power LDMOS transistors with customized thick oxide, " Microelectron. Rel., vols. 76–77, pp. 475–479, Sep. 2017.
[52] Moens, Peter, et al. "Hot hole degradation effects in lateral nDMOS transistors." IEEE Transactions on Electron Devices 51.10 (2004): 1704-1710.
[53] I. C. Chen, J. Y. Choi, T. Y. Chan, T. C. Ong and C. Hu, "The effect of channel hot carrier stressing on gate oxide integrity in MOSFET", 26th Proc. IEEE Reliability Phys. Symp., pp. 1-7, 1988-Apr.
[54] Wei Yao, Gennady Gildenblat, Colin C. McAndrew, Alexandra Cassagnes, "Compact Model of Impact Ionization in LDMOS Transistors", Electron Devices IEEE Transactions on, vol. 59, no. 7, pp. 1863-1869, 2012.
[55] Wang, Wenyuan, et al. "An accurate and robust compact model for high-voltage MOS IC simulation." IEEE transactions on electron devices 60.2 (2013): 662-669.