氧化鋅為寬能隙（3.3eV）n型半導體材料，具有多項優異特質且價格低廉使其被廣泛運用於各種用途中。氧化鋅因屬非對稱性結構而具有壓電特性，得以被用於製作壓電元件，例如：表面聲波元件、體聲波元件及由此兩種元件為基礎發展之通訊元件與感測元件。在壓電材料與其應用中，以往大量使用高壓電係數（d33）之鋯鈦酸鉛（PZT）等含有鉛元素之成分，近年人們因發現鉛對人體及環境的危害而捨棄含有鉛之材料，因此發展無鉛壓電材料替代PZT為現今的趨勢。
本實驗使用雙靶磁控共濺鍍系統沉積摻鐵氧化鋅薄膜於矽基板上，以提高薄膜之壓電係數。矽基板為半導體工業中最常使用之基板，選擇非壓電性之矽作為基板，雖無法利用壓電基板與壓電薄膜之間的交互作用來增加整體結構的壓電性，但因矽在CMOS製程上有高度相容性，故以未來發展之考量仍選擇矽為基材。實驗結果顯示，隨著鐵含量增加，氧化鐵鋅薄膜的d33值會增加，這是因為鐵離子置入鋅的晶格位置使薄膜顯微結構發生改變而使壓電性質有所提升。
具體而言，薄膜的C軸優選取向愈明顯，結晶性越好的結構，其壓電性質愈好。以雙靶射頻磁控共濺鍍沉積氧化鐵鋅薄膜，可成功沉積出具有高C軸取向之薄膜，且摻入鐵元素後薄膜之壓電係數也有明顯的提升，而d33最佳值為44.35pC/N出現於薄膜具有鐵含量為1.14 at. %時，約為未摻雜氧化鋅薄膜(13.04 pC/N)的4倍。
本研究亦對薄膜之顯微結構作探討，XRD結果顯示雙靶濺鍍可以成功製備C軸取向的氧化鋅摻鐵薄膜。隨著施加於氧化鐵靶的功率增加，薄膜中鐵含量增加在大於3.82 at. % 後，開始改變晶體結構之方式為使氧化鋅之（002）高C軸取向程度下降，並出現氧化鋅之（101）面及（100）面強度提升的趨勢。從SEM表面形貌亦可發現，在壓電係數最佳值(1.14 at. % Fe)時，薄膜具有較均勻的晶粒大小分布，而XPS對1.14 at. % Fe與3.82 at. % Fe的試片進行分析，結果顯示，壓電係數最佳值的試片(1.14 at. % Fe)中，鐵離子主要以+3的氧化態存在，而壓電係數急遽下降的試片(3.82 at. %)中，鐵則是主要以+2價出現，+2價與+3價之鐵離子半徑不同，因置換原本的晶格位置後，對結構造成不同程度的扭曲，使得壓電係數跟著提升與下降。

Fe-doped ZnO films are potential materials for acoustic wave devices because of its piezoelectric coefficient improvement gained from the substitution of Fe atoms for Zn sites which caused lattice distortion and induced a larger response in piezoelectricity. In this research, FexZn1-xO films were deposited by magnetron co-sputtering technique. The X-ray diffraction results showed highly c-axis preferred orientation FexZn1-xO films. SEM confirmed that the films are column-like and perpendicular to the substrate. Then, the piezoelectric coefficient (d33) was improved with the films. With Fe added into ZnO films, the optimal d33 value, 44.35 pC/N was achieved at 1.14 at. % Fe concentration.

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