本論文探討兩個主要研究課題。第一個研究課題是注入鎖定增強技術研究應用於CMOS注入鎖定除頻器 (Injection-locked Frequency Divider, ILFD)，該技術應用包括30 GHz除三除頻器和50 GHz除五除頻器。 該注入鎖定除頻器可應用於5G行動通信中的28 GHz和47 GHz頻段。第二個研究課題探討新型蜂巢狀平面電感應用於壓控振盪器 (Voltage-Controlled Oscillator, VCO) 的減緩注入牽引技術。
本論文第二章探討30 GHz注入鎖定除三除頻器電路設計採用注入開關交叉耦合對 (Injection-switched Cross-Coupled Pair, IS-CPP) 可增強鎖定範圍。此創新架構可以實現更寬鎖定範圍以及低電壓操作。該注入鎖定除頻器採用90 nm 標準CMOS製程，此注入除頻器電路設計的總鎖定範圍為4.5 GHz，電源電壓為0.5 V，直流功耗為2.85 mW。緩衝器的直流功耗為2.65 mW，電源電壓為1.0 V. 當30 GHz之輸入參考信號在1 MHz偏移的相位雜訊為 -131 dBc/Hz，量測之輸出相位雜訊為 -141 dBc/Hz。對於除三除頻器，10 dB的相位雜訊差距接近理論值9.5 dB。此注入鎖定除頻器晶片總面積為0.48 mm2，鎖定除頻器面積僅為0.14 mm2。
使用IS-CCP技術的CMOS 30 GHz注入鎖定除三除頻器也可以操作在除五模式，本論文第三章探討採用IS-CCP技術的該注入鎖定除五除頻器。相關的實驗結果證明了所提出的除頻器也可以作為50 GHz注入鎖定除五除頻器。此50 GHz注入鎖定除五除頻器的總鎖定範圍為2.4 GHz，總直流功耗為5.5 mW。當50 GHz之輸入信號在1 MHz偏移的相位雜訊為 -127 dBc/Hz，量測之輸出相位雜訊為 -143 dBc/Hz。該除頻器可應用於針對47 GHz無線通訊頻帶之毫米波鎖相迴路設計，其中包括新提出的5G行動通信頻段。
本論文的最後部分探討採用新型蜂巢狀平面電感器應用於壓控振盪器的減緩注入牽引技術。由於所提出的電感器中的特殊繞線佈局，可以補償和減少由附近的電磁雜訊源引起的干擾。透過使用0.18μm標準CMOS製程，所提出的蜂巢狀平面電感器和相近尺寸的傳統單匝螺旋電感器被整合到兩個相應的壓控振盪器測試晶片中，進行研究並比較這兩個壓控振盪器的注入牽引現象。實驗結果證明，與採用相近尺寸的傳統單匝電感器整合之壓控振盪器相比，與所提出的蜂巢狀平面電感器整合之壓控振盪器可以顯著減緩注入牽引現象。在這項研究中，可以實現超過15 dB的減緩注入牽引效果。

This dissertation covers two main research topics. The first main research topic is to study the injection locking enhancement technique in CMOS injection-locked frequency divider (ILFD), which includes the dual-band operation of 30 GHz divide-by-three and 50 GHz divide-by-five ILFD. The ILFD can be applied to the proposed 28 GHz and 47 GHz frequency bands of the 5G mobile communication. The second main topic is to study the injection pulling mitigation technique in CMOS LC voltage-controlled Oscillator using a novel honeycomb-shaped planar inductor.
The design of a divide-by-three frequency divider operating at 30 GHz with an injection- switched cross-coupled pair (IS-CPP) technique to enhance the locking range is reported in Chapter 2. A wider locking range as well as a lower operation voltage can be achieved because of this newly proposed topology. The divider is implemented in a 90 nm standard CMOS process. The total locking range of the divider core is 4.5 GHz with a power consumption of 2.85 mW from a supply voltage of 0.5 V. The total power consumption of the buffers is 2.65 mW from a supply voltage of 1.0 V. The measured output phase noise is -141 dBc/Hz at 1 MHz offset when the input referred signal with a phase noise of -131 dBc/Hz at 1 MHz offset from 30 GHz. The phase-noise difference of 10 dB is close to the theoretical value of 9.5 dB for division-by-three. The total chip size is 0.48 mm2 and the divider core size is only about 0.14 mm2.
A CMOS 30 GHz divide-by-three ILFD using the IS-CCP technique can also operate at a divide-by-5 mode. The related experimental results to demonstrate the extra capability of the proposed divider as a 50 GHz divide-by-five ILFD. The total locking range of 2.4 GHz is available at 50 GHz with a total dc power dissipation of 5.5 mW. The measured output phase noise of -143 dBc/Hz is obtained from an input signal of -127 dBc/Hz at 1 MHz offset from 50 GHz. This divider can be applied to a millimeter-wave PLL design for 47 GHz radio band applications, which include the newly proposed frequency band for the 5G mobile communication.
The last part of the dissertation presents the injection pulling mitigation technique applied to a voltage controlled oscillator (VCO) using a novel honeycomb-shaped planar inductor. Due to the twisted routes of the sub-coils in the proposed inductor, the interference caused by a nearby electromagnetic noise source can be compensated and reduced. By using a 0.18-μm standard CMOS process, the proposed honeycomb-shaped planar inductor and a conventional single-turn spiral inductor in a similar size are integrated into two respective VCO test chips. The injection pulling behaviors of these two oscillators are studied and compared. The experimental results show that the VCO integrated with the proposed honeycomb-shaped planar inductor can significantly mitigate the injection pulling phenomenon as compared to the VCO integrated with a conventional single-turn inductor in a similar size. In this study, the enhancement of mitigation over 15 dB can be achieved.

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