利用應變矽成長在矽鍺鬆弛基板上的技術而製作的電晶體是最具有前瞻性的技術之一。然而，矽鍺虛擬基板的品質卻受到鍺濃度漸變至高濃度所產生的差排累積而降低。在這篇論文裡，將探討抑制差排現象的製程策略，並且運用在矽基板上成長品質較好矽鍺鬆弛層結構。我們也試著找出在應變矽的互補式金氧半場效電晶體的最佳化通道工程以及製程整合方式。也將針對載子移動率提升和短通道效應(SCE)之間的取捨關係在不同厚度的矽覆蓋層及不同鍺含量的矽鍺鬆弛虛擬基板下進行研究。並證實閘極線寬為80奈米的應變矽元件能有效抑制短通道效應並且可以達到低缺陷密度。除此之外，在應變矽層之中過高的鍺含量擴散現象以及應力鬆弛效應將在直流及低頻雜訊的條件之下被研究；應變矽的N型金氧半場效電晶體 1/f雜訊的物理機制也同時被探討。

Strained silicon on relaxed silicon-germanium (SiGe) substrates is a promising candidate for transistor performance enhancement. However, the materials quality of SiGe virtual substrates degrades upon grading to high Ge concentrations due to the formation of threading dislocation pileups. In this thesis, growth strategy for the control and elimination of these dislocations is proposed and utilized to fabricate relaxed SiGe layers of good quality on Si. We also demonstrate optimized channel engineering and process integration in strained-Si CMOS technology. The trade-off between mobility enhancement and short channel effects (SCE) control for different Si-cap layer thickness and various Ge content in the relaxed-SiGe virtual substrate are investigated. A strained Si device with improved immunity to SCE and reduced defect density was demonstrated at gate length of 80 nm. Besides, Ge out-diffusion and strain relaxation effect in strained-Si layer are studied in both DC and low frequency (1/f) noise. The 1/f noise mechanism of strained-Si nMOSFETs has been investigated.

Chapter 1
[1]G. E. Moore, “ Gramming More components onto integrated circuits,” Electronics 38, 1965.
[2]B. Yu, H. Wang, C. Riccobene, Q. Xiang; M. R. Lin,” Limits of gate-oxide scaling in nano-transistors,” VLSI symp., pp. 90-91, 2000.
[3]L.-A. Ragnarsson, L. Pantisano, V. Kaushik, S.-I. Saito, Y. Shimamoto, S. D. Gendt, M. Heyns, “The impact of sub monolayers of HfO/sub/ on the device performance of high-k based transistors,” IEDM Tech. Dig. pp. 4.2.1 - 4.2.4, 2003.
[4]D. A. Dallmann, K. Shenai, “Scaling constraints imposed by self-heating in submicron SOI MOSFET's,” IEEE Trans. Electron Dev. Vol. 42, 3, pp. 489 - 496, 1995.
[5]T. Mizuno, S. Takagi, N. Sugiyama, H. Satake, A. Kurobe, and A. Toriumi, “ Electron and hole mobility enhancement in strained-Si MOSFET’s on SiGe-on-Insulator substrates fabricated by SIMOX technology,” IEEE Electron Dev. Lett., vol. 21, pp. 230-232, 2000.
[6]M. L. Lee, and E. A. Fitzgerald, “Hole mobility enhancements in nanometer-scale strained-Silicon heterostructures grown on Ge-rich relaxed Si1-xGex,” J. Appl. Phys. 94, pp. 2590-2596, 2003.
[7]K. Rim, J. Chu, H. Chen, KA Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, J. Newbury, J. Ott, K. Petrarca, P. Mooney, D. Lacey, S. Koester, K. Chan, D. Boyd, M. Ieong, and HS Wong, “Characteristics and device and design of sub-100nm strained Si N- and PMOSFETs,” VLSI symp., pp. 98-99, 2002.
[8]N. Sugii, D. Hisamoto, K. Washio, N. Yokoyama, S. Kimura, “Performance enhancement of strained-Si MOSFETs fabricated on a chemical-mechanical-polished SiGe substrate,” IEEE Trans. Electron Dev. vol. 49, 12, pp. 2237-2243, 2002.
[9]S. Eguchi, J. L. Hoyt, C. W. Leitz and E. A. Fitzgerald, “Comparison of arsenic and phosphorus diffusion behavior in silicon–germanium alloys “ Appl. Phys. Lett. 80, pp. 1743, 2002.
[10]J. G. Fiorenza, G. Braithwaite, C. Leitz, M. T. Currie, Z. Y. Cheng, V. K. Yang, T. Langdo, J. Carlin, M. Somerville, A. Lochtefeld, H. Badawi, M. T. Bulsara, “Investigation of misfit dislocation leakage in supercritical strained silicon MOSFETs ,“ IRPS, pp. 493, 2004.
[11]W. Jin, S. K. H. Fung, W. Liu, P. C. H. Chan and C. Hu, “Self-heating characterization for SOI MOSFET based on AC output conductance,” IEDM Tech. Dig. pp. 175, 1999

Chapter 2
[1]R. People, “Physical and applications of GexSi1-x/Si strained-layer heterostructures, ” IEEE Journal of Quantum Electronics, vol. QE-22, NO. 9, pp.1696, 1986.
[2]J. H. van der Merwe, “Crystal interface. Part II. Finite Overgrowths,” Journal of Applied Physics, vol. 34, pp. 123, 1963.
[3]Y. H. Xie, “SiGe field effect transistors,” Materials Science and Engineering, vol. 25, pp. 89, 1999.
[4]M. P. Temple, D. J. Paul, Y. T. Tang, and A. M. Waite, “Compressively-strained, buried-channel Si0.7Ge0.3 p-MOSFETs fabricated on SiGe virtual substrates using a 0.25μm CMOS process,” IEEE Electron Dev. Lett., 2004
[5]R. Braunstein, A. R. Moore, and F. Herman, “Intrinsic Optical Absorption in Germanium-Silicon Alloys,” Phys. Rev. 109, pp. 695, 1958
[6]D. V. Lang, R. People, J. C. Bean, and A. M. Sergent, “Measurement of the band gap of GexSi1−x/Si strained-layer heterostructures,” Appl. Phys. Lett. 47, pp. 1333, 1985
[7]D. K. Nayak and S. K. Chun, “Low-field hole mobility of strained Si on (100) Si1–xGex substrate,” Appl. Phys. Lett. 64, pp. 2514, 1994
[8]T. Vogelsang and K. R. Hofmann, “Electron transport in strained Si layers on Si1−x Gex substrate, “ Appl. Phys. Lett. 63, pp. 186, 1993
[9]R. People, J. C. Bean, D. V. Lang, A. M. Sergent, and H. L. Stormer ,K. W. Wecht, R. T. Lynch, and K. Baldwin, “Modulation doping in GexSi1-x/Si strained layer heterostructures,” Appl. Phys. Lett. 45, pp. 1231, 1984
[10]M. M. Rieger and P. Vogl, “Electronic-band parameters in strained Si1-xGex alloys on Si1-yGey substrates,” Phys. Rev. B 48, pp. 14276, 1993
[11]S. Subbanna, G. Freeman, D. Ahlgren, D. Greenberg, D. Harame, J. Dunn, D.
Herman, B. Meyerson, Y. Greshishchev, P. Schvan, D. Thornberry, D. Sakamoto, and R. Tayrani, ”Integration and Design Issues in Combining Very-High-Speed Silicon-Germanium Bipolar Transistors and ULSI CMOS for System-on-a-Chip Applications,” IEDM Tech. Dig., pp. 845, 1999
[12]T. E. Whall and E. H. C. Parker, “SiGe—Heterostructures for CMOS technology,” Thin Solid Films 367, pp. 250, 2000
[13]G.Hock, T. Hackbarth, U. Erben, E. Kohn, and U. Konig, “High performance 0.25um p-type Ge/SiGe MODFET’s,” Electron. Lett. 34, pp. 1888, 1998
[14]G. Abstreiter, H. Bragger, T. Wolf, H. Jorke, and H. J. Herzog, “Strain-Induced Two-Dimensional Electron Gas in Selectively Doped Si/SixGe1-x Superlattices,” Phys. Rev. Lett. 54, pp. 2441, 1985
[15]J. Welser, J. L. Hoyt, S. Takagi, and J. F. Gibbons, “Strain dependence of the performance enhancement in strained-Si n-MOSFETs,” IEDM Tech. Dig., pp. 373 , 1994
[16]K. Ismail, S. F. Nelson, J. O. Chu, and B. S. Meyerson, “Electron transport properties of Si/SiGe heterostructures: Measurements and device implications,” Appl. Phys. Lett. 63, pp. 660, 1993
[17]N. Sugii, K. Nakagawa, Y. Kimura, S. Yamaguchi, and M. Miyao, “High Electron Mobility in Strained Si Channel of Si1-xGex/Si/Si1-xGex Heterostructure with Abrupt Interface,” Semicond. Sci. Technol. 13, pp. A140, 1998
[18]J. Weiser, J. L. Hoyt, and J. F. Gibbons, “Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors,” IEEE Electron Dev. Lett. 15, pp. 100, 1994
[19]D. K. Nayak, J. C. S. Woo, J. S. Park, K. L. Wang, and K. P. MacWilliams, “High-mobility p-channel metal-oxide-semiconductor field-effect transistor on
strained Si,” Appl. Phys. Lett. 62, 2853, 1993
[20]T. Yamada, J.-R. Zhou, H. Miyata, and D. K. Ferry, “In-plane transport properties of Si/Si1-xGex structure and its FET performance by computer simulation,” IEEE Trans. Electron Dev. 41, 1513 (1994).
[21]F. M. Bufler and B. Meinerzhagen, “Hydrodynamic transport parameters for holes in strained silicon,” Proceedings of the Sixth International IEEE Workshop on Computational Electronics, pp. 242, 1998
[22]K. Rim, J. L. Hoyt, and J. F. Gibbons, “Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFET’s,” IEEE Trans. Electron Dev. 47, pp. 1406, 2000

Chapter 3
[1]B. S. Meyerson, “Low-temperature silicon epitaxy by ultrahigh vacuum/chemical vapor deposition,” Appl. Phys. Lett. 48, pp. 797, 1986
[2]D. J. Robbins, J. L. Glasper, A. G. Cullis, and W. Y. Leong, “A model for heterogeneous growth of Si1–xGex films from hydrides,” J. Appl. Phys. 69, pp. 3729, 1991
[3]C. Tsai, S. M. Jang, J. Tsai, and R. Rief, “Growth and characterization of undoped and in situ doped Si1–xGex on patterned oxide Si substrates by very low pressure chemical vapor deposition at 700 and 625 °C,” J. Appl. Phys. 69, pp. 8158, 1991
[4]B. S. Meyerson, “UHV/CVD growth of Si and Si:Ge alloys: chemistry, physics, and device applications,” Proc. IEEE 80, pp. 1592, 1992
[5]D. W. Greve, “Growth of epitaxial germanium-silicon heterostructures by chemical vapour deposition,” Mater. Sci. Eng. B 18, pp. 22, 1993
[6]F. W. Smith and G. Ghidini, “Reaction of Oxygen with Si(111) and (100):Critical
Conditions for the Growth of SiO2,” J. Electrochem. Soc. 129, pp. 1300, 1982
[7]G. Ghidini and F. W. Smith, “Interaction of H2O with Si [111] and Si [100]. Critical conditions for the growth of SiO2,” J. Electrochem. Soc. 131, pp. 2924, 1984
[8]D. G. Schimmel, “Defect etch for <100> silicon evaluation,” J. Electrochem. Soc. 126, pp. 479, 1979
[9]C. G. Tuppen and C. J. Gibbings, “Misfit dislocations in annealed Si1−xGex/Si heterostructures,” Thin Solid Films 183, pp. 133, 1989
[10]J. M. Baribeau, T. E. Jackman, D. C. Houghton, P. Maigne, and M. W. Denhoff, “Growth and characterization of Si1–xGex and Ge epilayers on (100) Si,” J. Appl. Phys. 63, pp. 5738, 1988
[11]E. A. Fitzgerald, Y.-H. Xie, M. L. Green, D. Brasen, A. R. Kortan, J. Michel, Y.-J. Mii, and B. E. Weir, “Totally relaxed GexSi1–x layers with low threading dislocation densities grown on Si substrates,” Appl. Phys. Lett. 59, pp. 811, 1991
[12]E. A. Fitzgerald, Y. H. Xie, M. L. Green, D. Brasen, A. R. Kortan, Y. J. Mii, J. Michl, B. E. Weir, L. C. Feldman, and J. M. Kuo, “Strain-Free GexSi1-x Layers with Low Threading Dislocation Densities Grown on Si strates,” Mater. Res. Soc. Symp. Proc. pp. 220, 1991
[13]P. M. Mooney, “Strain relaxation and dislocations in Si/iSiGe structure,” Mater. Sci.
[14]K. Rim et al., “Fabrication and analysis of deep submicron strained-Si n-MOSFETs”, IEEE Trans. Elect. Dev. 47, pp. 1406, 2000.
[15]T. Tezuka et al., “Fabrication of strained Si on an ultrathin SiGe-on-insulator virtual substrate with a high-Ge fraction”, Appl. Phys. Lett. 79, pp. 1798, 2001.
[16]A. R. Powell et al., “New approach to the growth of low dislocation relaxed SiGe material”, Appl. Phys. Lett. 64, pp. 1856, 1994.
[17]P. S. Chen, S. W. Lee, M. H. Lee, and C. W. Liu, “Growth of high-quality relaxed SiGe films with an intermediate Si layer for strained Si n-MOSFETs”, Semicond. Sci. Technol., vol. 21, p. 479, 2006.

Chapter 4
[1]Hua W C, Lee M H, Chen P S, Maikap S, Liu C W and Chen K M, ”Ge outdiffusion effect on flicker noise in strained-Si nMOSFETs,” IEEE Electron Device Lett., vol. 25 693, 2004
[2]Louch T, Chen C S, Yang L W, Shih H H, Chen K C, Hsueh C, Chung H, Pan S and Lu C Y, “Stress release for shallow trench isolation by single-wafer, rapid-thermal steam oxidation,” International Conference on Advanced Thermal Processing of Semiconductors, pp. 111, 2002.
[3]Fiorenza J G, Braithwaite G, Leitz C, Currie M T, Cheng Z Y, Yang V K, Langdo T, Carlin J, Somerville M, Lochtefeld A, Badawi H, Bulsara M T, “Investigation of misfit dislocation leakage in supercritical strained silicon MOSFETs,” International Reliability Physics Symp., pp. 493, 2004
[4]J. Lutze, T. Miranda, G. Scott, C. Olsen, N. Variam, and S. Mehta, “Optimization of implant anneals to improve transistor performance in a 0.15 μm CMOS technology,” IEEE Electron Dev. Lett., vol. 21, pp. 451 (2000).
[5]F. Schäffler, “High-mobility Si and Ge structures,” Semicond. Sci. Technol, vol. 12, pp.1515-1549, 1997
[6]E. A. Fitzgerald, Y-H. Xie, M. L. Green, D. Brasen, A. R. Kortan, J. Micael, Y-J. Mii, and B. E. Weir “Oxidation-induced traps near SiO2/SiGe interface,” Appl. Phys. Lett., vol. 86, pp. 1542-1545, 1999
[7]K. Rim, J. Chu, H. Chen, KA Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, J. Newbury, J. Ott, K. Petrarca, P. Mooney, D. Lacey, S. Koester, K. Chan, D. Boyd, M. Ieong, and HS Wong, “Characteristics and device and design of sub-100nm strained Si N- and PMOSFETs,” VLSI symp., pp. 98-99, 2002
[8]M. C. Öztϋrk, J. Liu, and H. Mo, “Low resistivity nickel germanosilicide contacts to ultra-shallow SiGe source/drain junctions for nanoscale CMOS,” IEDM Tech. Dig., pp. 497-500, 2003
[9]C. P. Chao, K. E. Violette, S. Unnikrishnan, M. Nandakumar, R. L. Wise, J. A. Kittl, Q. Z. Hong, and I. C. Chen “Low resistance Ti or Co salicided raised source/drain transistors for sub-0.13μm CMOS technologies,” VLSI symp., pp. 97-103, 1997
[10]K. Terada and H. Muta, “ new method to determine effective MOSFET channellength,” Jap. J. Appl. Phys., vol. 18, p. 953, 1979
[11]J. G. J. Chern, P. Chang, R. F. Motta, and N. Godinho,” new method to determine MOSFET channel length,” IEEE Electron Dev. Lett., p.170, 1980
[12]J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald, and D. A. Antoniadis, “Strained Silicon MOSFET Technology,” VLSI symp., pp. 23-26, 2002

Chapter 5
[1]G. K. Dalapati, S. Chattopadhyay, K. S. K. Kwa, S. H. Olsen, Y. L. Tsang, R. Agaiby, A. G. O’Neill, P. Dobrosz, and S. J. Bull, “Impact of Strained-Si Thickness and Ge Out-Diffusion on Gate Oxide Quality for Strained-Si Surface Channel n-MOSFETs,” IEEE Trans. Electron Devices, vol. 53, no. 5, p. 1142, Jan. 2006.
[2]C. C. Yeo, B. J. Cho, M. H. Lee, C. W. Liu, K. J. Choi, and T. W. Lee, “Thermal stability study of Si cap/ultrathin Ge/Si and strained Si/Si1-xGex/Si nMOSFETs with HfO2 gate dielectric,＂Semicond. Sci. Technol., vol. 21, pp. 665, 2006.
[3]R. Loo, R. Delhougne, M. Caymax, and M. Ries, “Formation of misfit dislocations at the thin strained Si/strain-relaxed buffer interface,” Appl .Phys. Lett., vol.87, no. 18, pp. 182108, Oct. 2005.
[4]M. T. Currie, C. W. Leitz, T. A. Langdo, G. Taraschi, and E. A. Fitzgerald, “Carrier mobilities and process stability of strained-Si n and p-MOSFETs on SiGe virtual substrates,” J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol. 19, no. 6, pp. 2268, 2001.
[5]T. Mizuno, N. Sugiyama, T. Tezuka, T. Maeda, and S. Takagi, “Design for scaled thin films strained-SOI CMOS devices with higher carrier mobility,” in IEDM Tech. Dig. , pp. 31, 2002
[6]W. A. Hill, and C. C. Coleman, “A single frequency approximation for interface-state density determination,” Solid State Electron., vol. 23, no. 9, pp. 987, 1980.
[7]S. H. Olsen, A. G. O’Neill, L. S. Driscoll, S. Chattopadhyay, K. S. K. Kwa, A. M. Waite, Y. T. Tang, A. G. R. Evans, and J. Zhang, “Optimization of Alloy Composition for High-Performance Strained-Si–SiGe N-Channel MOSFETs,” IEEE Trans. Electron Devices, vol. 51, no. 7, pp. 1156, Jul. 2004.
[8]J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald, and D. A. Antoniadis, “Strained Silicon MOSFET Technology,” VLSI symp., pp. 23, 2002
[9]J. S. Goo, Q. Xiang, Y. Takamura, F. Arasnia, E. N. Paton, P. Besser, J. Pan, and M. R. Lin, “Band Offset Induced Threshold Variation in Strained-Si nMOSFETs,” IEEE Trans. Electron Devices Lett., vol. 24, no. 9, pp. 568-579, Sep. 2003.
[10]R. People, and J. C. Bean “Calculation of critical layer thickness versus lattice mismatch for GexSi1–x/Si strained-layer heterostructures,＂Appl .Phys. Lett., vol.47, no. 3, pp. 322-324, 1 Aug.1985.
[11]R. Oberhuber, G. Zandler, and P. Vogl, “Subband structure and mobility of two-dimensional holes in strained Si/SiGe MOSFET’s,” Phys. Rev. B, vol. 58, pp. 9941-9948, 1998.
[12]S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr and Y. E. Mansy: IEEE Electron Dev. Lett., vol. 25 pp. 191, 2004
[13]T. Y. Lu and T. S. Chao, “Mobility enhancement in local strain channel nMOSFETs by stacked a-Si/poly-Si gate and capping nitride,” IEEE Electron Dev. Lett., vol. 26, no. 4, pp. 267-269, 2000.
[14]Y. M. Lin, S. L. Wu, S. J. Chang, P. S. Chen and C. W. Liu, “SiGe/Si PMOSFET using graded channel technique,” Materials Science in Semiconductor Processing, vol. 8, pp. 347-351, 2005.
[15]P. W. Li and W. M. Liao, “Analysis of Si/SiGe channel pMOSFETs for deep-submicron scaling,” Solid State Electron, vol. 46, pp. 39-44, 2002.
[16]J. Jung, M. L. Lee, S Yu, E. A. Fitzgerald and D.A. Antoniadis, “Implementation of both high-hole and electron mobility in strained Si/strained Si1-yGey on relaxed Si1-xGex (x < y) virtual substrate,” IEEE Electron Dev. Lett., vol. 24, no. 7, pp. 460-462, Jul. 2003.
[17]E. Josse and T. Skotnicji, “Polysilicon gate with depletion-or-metallic gate with buried channel what evil worse ?,” IEDM Tech. Dig., pp. 661-664, 1999.
[18]J. G. Fiorenza, G. Braithwaite, C. Leitz, M. T. Currie, Z. Y. Cheng, V. K. Yang, T. Langdo, J. Carlin, M. Somerville, A. Lochtefeld, H. Badawi, M. T. Bulsara, “Investigation of misfit dislocation leakage in supercritical strained silicon MOSFETs,” IRPS, pp. 493-497, 2004.
[19]M. T. Currie, T. A. Langdo , G. Taraschi , E. A. Fitzgerald, D. A. Antoniadis, “Carrier mobilities and process stability of strained Si n- and p-MOSFETs on SiGe virtual substrates,” J. Vacuum. Sci. Technol. B, pp. 2268-2279, 2001.
[20]M. Somerville, “Hyperspectral imaging of breakdown in InAlAs/InGaAs HEMTs: a comparative study,” in Device Research Conference Confeence Digest, pp, 65 – 66, 2001.
[21]W. Jin, S. K.-H. Fung, W. Liu, P. C.-H. Chan, and C. Hu, “Self-Heating Characterization for SOI MOSFET Based on AC Output Conductance,” IEDM Tech. Dig., pp. 175-179, 1999.

Chapter 6
[1]A.L. McWhorter et al., in Semiconductor Surface Physics, edited by R.H. Kingston (University of Pennsylvania, Philadelphia, 1957) pp. 207-228.
[2]E. Simoen, and C. Claeys, “On the flicker noise in submicron silicon MOSFETs,” Solid-State Electron., vol. 43, pp. 865-882, 1999.
[3]G. Ghibaudo, and T. Boutchacha, “Electrical noise and RTS fluctuations in advanced CMOS devices,” Microelectron. Reliab., vol. 42, pp. 573-582, 2002.
[4]L. K. J. Vandamme, X. Li, and D. Rigaud, “1/f noise in MOS devices, mobility or number fluctuations,” IEEE Trans. Electron Devices, vol. 41, pp. 1936-1945, 1994.
[5]J. Chang, A. A. Abidi, and C. R. Viswanathan, “Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures,” IEEE Trans. Electron Devices, vol. 41, pp. 1965-1971, 1994.
[6]B. Cretu, M. Fadlallah, G. Ghibaudo, J. Jomaah, F. Balestra, and G. Guégan, “Thorough characterization of deep-submicron surface and buried channel pMOSFETs,” Solid-State Electron, pp. 97 1-975, 2002.
[7]A. van der Ziel, “Unified presentation of 1/f noise in electronic devices: fundamental 1/f noise sources,” Proc. IEEE, vol. 76, pp. 233-258, 1988.
[8]S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, T. Numata, K. Usuda, Y. Moriyama, S. Nakaharai, and M. Koga, “Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-On-Insulator (Strained-SOI) MOSFET”, IEDM Tech. Dig., pp. 57-60, 2003.
[9]S. L. Wu, Y. P. Wang, and Shoou Jinn Chang, “Controlled misfit dislocation technology in strained silicon MOSFETs”, Semicond. Sci. Technol., vol 21, pp. 44-47, 2006.
[10]W.-C. Hua, M. H. Lee, P. S. Chen, S. Maikap, and C. W. Liu, ”Ge outdiffusion effect on flicker noise in strained-Si nMOSFETs”, IEEE Electron Device Lett.s, vol. 25, pp. 693-695, 2004.
[11]E. Simoen, G. Eneman, P. Verheyen, R. Delhougne, R. Loo, K. De Meyer, and C. Claeys, “On the beneficial impact of tensile-strained silicon substrates on the low-frequency noise of n-channel metal-oxide-semiconductor transistors”, Appl. Phys. Lett., vol. 86, 2005
[12]W.-C. Hua, M. H. Lee, P. S. Chen, S. Maikap, and C. W. Liu, ”Threading dislocation induced low frequency noise in strained-Si nMOSFETs”, IEEE Electron Device Lett., vol. 25, pp. 667-669, 2005.
[13]G. Ghibaudo, O. Roux, C. Nguyen-Duc, F. Balestra, and J. Brini, “Improved analysis of low frequency noise in field-effect MOS transistors,” Phys. Status Solidi, A Appl. Res., vol. 124, no. 2, pp. 571–581, Apr. 1991.
[14]G. Ghibaudo and T. Boutchacha, “Electrical noise and RTS fluctuations in advanced CMOS devices,” Microelectron Reliab., vol. 42, no. 4/5, pp. 573–582, 2002.
[15]A. L. McWhorter, Secomductor surface physics, R. H. Kinston, Ed. Philadelphia, PA: Univ. Penn., 1957.
[16]J. G. Fiorenza, G. Braithwaite, C. W. Leitz, M. T. Currie, J. Yap, F. Singaporewala, V. K. Yang, T. A. Langdo, J. Carlin, M. Somerville, A. Lochtefeld, H. Badawi, and M. T. Bulsara, “Film thickness constraints for manufacturable strained silicon CMOS”, Semicond. Sci. Technol. vol. 19, pp. L4-L8, 2004.
[17]G. Ghibaudo, and T. Microelectron, ”Electrical noise and RTS fluctuations in advanced CMOS devices,” Microelectron Reliab, vol. 42, pp. 573-582, 2002.
[18]K. K. Hung, P. K. Ko, C. Hu, Y. C. Cheng. “A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistor,” IEEE Trans. Electron Devices, vol. 37, pp. 654-665, 1990.

Chapter 7
[1]G. Scott, J Lutze, M Rubin, F Nouri, M Manley, “NMOS drive current reduction caused by transistor layout and trench isolation induced stress”, IEDM Tech. Dig., pp. 827 - 830, 1999
[2]T Matsumoto, S Maeda, H Dang, T Uchida, K Ota, Y Hirano, H Sayama, T Iwamatsu, T Ipposhi, H Oda, S Maegawa, Y Inoue, T Nishimura, “Novel SOI wafer engineering using low stress and high mobility CMOSFET with <100>-channel for embedded RF/analog applications”, IEDM Tech. Dig., pp. 663 - 667, 2002
[3]A. Steegen, M Stucchi, A Lauwers, K Maex, “Silicide induced pattern density and orientation dependent transconductance in MOS transistors“, IEDM Tech. Dig., pp. 497 - 500, 1999
[4]A. Shimizu, K Hachimine, N Ohki, H Ohta, M Koguchi, Y Nonaka, H Sato, F Ootsuka, “Local mechanical-stress control (LMC): a new technique for CMOS-performance enhancement”, IEDM Tech. Dig., pp. 433 - 436, 2001
[5]C. H. Ge, C. C. Lin, C. H. KO, C. C. Huang, Y. C. Huang, B. W. Chan, B. C. Pemg, C. C. Sheu, P. Y. Tsai, L. G. Yao, C. L. Wu, T. L. Lee, C. J. Chen, C. T. Wang, S. C. Lin, Y. C. Yeo and C. Hu, ”Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering”, IEDM Tech. Dig., pp. 73 - 76, 2003