隨著次世代通訊技術與毫米波雷達的蓬勃發展，高效能頻率合成技術成為決定系統動態範圍與測距精度的核心指標，然而直接在高頻段實現鎖相迴路常面臨電感品質因子下降及除頻器功耗過大的技術瓶頸。本論文針對此問題提出了一種以輸出 4.8 GHz 為系統頻譜基準的頻率架構，並採用TSMC 0.18 μm CMOS製程實現兩項核心電路之設計，分別是用於4.8 GHz頻段的壓控振盪器，以及專為低功耗ISM頻段開發的2.4 GHz三角積分調變器小數型鎖相迴路。這種架構設計理念透過中繼頻率(2.4 GHz)的共用與倍頻電路(×2)的整合，使系統不僅能同步衍生出 2.4 GHz 收發機所需的本地振盪訊號，亦能提供4.8 GHz輸出頻率，在維持低功耗的前提下，有效節省單晶片系統(SoC)整合時的面積與成本。
本論文針對高性能頻率合成技術提出兩項研究成果。第一部分為一應用於24 GHz雷達參考訊號之4.8 GHz壓控振盪器(Voltage controlled oscillator, VCO)。該設計採用TSMC 0.18 μm CMOS 製程，電路採用動態基底偏壓(Dynamic body-biasing)機制。相較於傳統Class-B技術易使電晶體進入深線性區並劣化相位雜訊之缺點，本設計在固定閘極偏壓下，透過提升基極電壓降低交叉耦合電晶體之臨界電壓，進而放寬起振條件並有效補償電感電容共振腔阻。電容電感共振腔部分採用中央抽頭式電感，並對其尺寸優化，以提升品質因子，而電容使用分散式電容陣列與切換電容陣列使操作頻率涵蓋4.481 GHz 至 4.962 GHz。量測結果顯示，該振盪器在功耗12.7 mW下，實現了10.2%的頻率調諧範圍，相位雜訊表現於1 MHz偏移頻率下達-121.72 dBc/Hz，整體壓控振盪器FoM (Figure of merit)為-184.3。
論文第二部分探討一款專為低功耗ISM頻段開發之2.4 GHz小數型鎖相迴路 (Fractional-N PLL)。該架構利用三角積分調變器(DSM)執行雜訊整形，藉由動態調變除頻器之除數，將低頻量化雜訊推移至迴路濾波器頻寬外的高頻區域再由三階被動式迴路濾波器進行有效濾除。為了解決充電泵電流不匹配導致的雜訊折疊效應，電路中引入了高匹配特性的動態電流匹配充電泵，並搭配具備二位元切換電容陣列的互補式 VCO，以降低壓控增益並抑制控制端與供應電壓端貢獻之雜訊。此晶片同樣基於 TSMC 0.18 μm CMOS製程，面積為1.472{mm}^2。在6.4 mW的功耗下，該 PLL於量測時之各輸出頻率皆高於3 dBm的輸率，其方均根抖動(RMS Jitter)為2.79 ps，以及1MHz偏移頻率之下相位雜訊 -104.02 dBc/Hz。本論文在低功耗與高訊號品質間達成理想折衷，為次世代無線收發器提供了具競爭力的設計方案。

This thesis is divided into two primary research components focusing on high-performance frequency synthesis design. The first part presents a 4.8 GHz voltage-controlled oscillator (VCO) integrated with dynamic body-biasing technique, designed as the fundamental reference signal for 24 GHz radar systems. Rather than adopting the conventional Class-B type of increasing bias—which tends to push transistors into the deep triode region during steady-state and consequently degrades phase noise—this design maintains a fixed gate bias while incorporating dynamic body-biasing to modulate the threshold voltage (V_{th}). By applying a forward body bias, the threshold voltage of the cross-coupled pair is effectively reduced as the body voltage rises. This bias way relaxes the startup conditions, allowing the circuit to efficiently compensate for tank losses and achieve stable oscillation.
The chip in the first part is fabricated in a TSMC 0.18 μm CMOS process, and the total area is about 0.779 {mm}^2. This VCO achieves a 10.2% tuning range (4.481~4.962 GHz) and a peak tuning sensitivity (K_{VCO}) of 227 MHz/V. Experimental results demonstrate a phase noise of -121.72 dBc/Hz at a 1 MHz offset and an output power of about -5~-7 dBm. Despite a marginal 3 dBc lower than the simulation results at higher frequency range due to external interference, the design maintains a competitive figure of merit (FoM) of -184.3 with a power consumption of 12.7 mW.
The second part details a 2.4 GHz fractional-N phase-locked loop (PLL) design optimized for low-power ISM-band applications. The proposed PLL architecture leverages a Delta-Sigma Modulator (DSM) to redistribute close-in noise power density via noise-shaping. By continuously modulating the frequency divider's modulus, the DSM shifts the quantization noise—originally concentrated at low frequencies with periodic signatures—into a high-frequency region beyond the loop filter's bandwidth.
The chip in the second part is also implemented in TSMC 0.18μm CMOS technology, the total area is about 1.472{mm}^2. This PLL covers the frequency range of 2.353~2.482 GHz with a 4.598 MHz resolution, exhibiting stable lock at the desired frequency across all division ratios. The system delivers an optimal phase noise of -104.02 dBc/Hz at a 1 MHz offset and an integrated RMS jitter of 2.79 ps. Operating at 6.4 mW with an output power exceeding 3 dBm, this design successfully harmonizes stringent power constraints with high signal integrity, providing an efficient solution for next-generation wireless transceivers.

[1] Skolnik, M. I. (1980). Introduction to radar systems (Vol. 3, pp. 81-92). New York: McGraw-hill.
[2] T. Siriburanon, W. Deng, K. Okada and A. Matsuzawa, "A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits," 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, 2014, pp. 25-26, doi: 10.1109/ASPDAC.2014.6742856.
[3] L. Fanori and P. Andreani, "Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs," in IEEE Journal of Solid-State Circuits, vol. 48, no. 7, pp. 1730-1740, July 2013, doi: 10.1109/JSSC.2013.2253402.
[4] K. Okada, Y. Nomiyama, R. Murakami and A. Matsuzawa, "A 0.114-mW dual-conduction class-C CMOS VCO with 0.2-V power supply," 2009 Symposium on VLSI Circuits, Kyoto, Japan, 2009, pp. 228-229.
[5] T. -P. Wang and C. -C. Li, "A 0.4-V 1.08-mW 12-GHz high-performance VCO in 0.18-µm CMOS," 2012 IEEE Radio and Wireless Symposium, Santa Clara, CA, USA, 2012, pp. 207-210, doi: 10.1109/RWS.2012.6175356.
[6] J. Chen, F. Jonsson, M. Carlsson, C. Hedenas and L. -R. Zheng, "A Low Power, Startup Ensured and Constant Amplitude Class-C VCO in 0.18 CMOS," in IEEE Microwave and Wireless Components Letters, vol. 21, no. 8, pp. 427-429, Aug. 2011, doi: 10.1109/LMWC.2011.2160620.
[7] J. -H. Song, B. -S. Kim and S. Nam, "An Adaptively Biased Class-C VCO With a Self-Turn-Off Auxiliary Class-B Pair for Fast and Robust Startup," in IEEE Microwave and Wireless Components Letters, vol. 26, no. 1, pp. 34-36, Jan. 2016, doi: 10.1109/LMWC.2015.2505637.
[8] M. Tohidian, A. Fotowat-Ahmadi, M. Kamarei and F. Ndagijimana, "High-swing class-C VCO," 2011 Proceedings of the ESSCIRC (ESSCIRC), Helsinki, Finland, 2011, pp. 495-498, doi: 10.1109/ESSCIRC.2011.6045015.
[9] W. Deng, K. Okada and A. Matsuzawa, "Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing," in IEEE Journal of Solid-State Circuits, vol. 48, no. 2, pp. 429-440, Feb. 2013, doi: 10.1109/JSSC.2012.2227603.
[10] P. Shasidharan, H. Ramiah and J. Rajendran, "A 2.2 to 2.9 GHz Complementary Class-C VCO With PMOS Tail-Current Source Feedback Achieving – 120 dBc/Hz Phase Noise at 1 MHz Offset," in IEEE Access, vol. 7, pp. 91325-91336, 2019, doi: 10.1109/ACCESS.2019.2927031.
[11] S. E. Meninger and M. H. Perrott, "A 1-MHZ bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise," in IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp. 966-980, April 2006, doi: 10.1109/JSSC.2006.870894.
[12] H. Sunami, K. Shimohigashi and N. Hashimoto, "An optically defined 1.3-µm NMOS ring oscillator," in IEEE Electron Device Letters, vol. 4, no. 9, pp. 311-313, Sept. 1983, doi: 10.1109/EDL.1983.25745.
[13] M. Esmaeilzadeh, Y. Audet, M. Ali and M. Sawan, "A Low-Phase-Noise CMOS Ring Voltage-Controlled Oscillator Intended for Time-Based Sensor Interfaces," in IEEE Access, vol. 10, pp. 101186-101197, 2022, doi: 10.1109/ACCESS.2022.3208273.
[14] D. B. Leeson, "A simple model of feedback oscillator noise spectrum," in Proceedings of the IEEE, vol. 54, no. 2, pp. 329-330, Feb. 1966, doi: 10.1109/PROC.1966.4682.
[15] A. Mazzanti and P. Andreani, "A Push–Pull Class-C CMOS VCO," in IEEE Journal of Solid-State Circuits, vol. 48, no. 3, pp. 724-732, March 2013, doi: 10.1109/JSSC.2012.2230542.
[16] J. -W. Moon, K. -C. Choi and W. -Y. Choi, "A 0.4-V, 90 350-MHz PLL With an Active Loop-Filter Charge Pump," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 5, pp. 319-323, May 2014, doi: 10.1109/TCSII.2014.2312800.
[17] M. H. Perrott, M. D. Trott and C. G. Sodini, "A modeling approach for Σ-Δ fractional-N frequency synthesizers allowing straightforward noise analysis," in IEEE Journal of Solid-State Circuits, vol. 37, no. 8, pp. 1028-1038, Aug. 2002, doi: 10.1109/JSSC.2002.800925.
[18] Biswas, Debdut, and Tarun Kanti Bhattacharyya. "Causes of PLL spurs and their modeling." Analog Integrated Circuits and Signal Processing 100.3 (2019): 639-652.
[19] S. Pamarti, L. Jansson and I. Galton, "A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation," in IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 49-62, Jan. 2004, doi: 10.1109/JSSC.2003.820858.
[20] J.-S. Lee, M.-S. Keel, S.-I. Lim, and S. Kim, "Charge pump with perfect current matching characteristics in phase-locked loops," Electronics Letters, vol. 36, no. 23, pp. 1907–1908, Nov. 2000, doi: 10.1049/el:20001358.
[21] M.-S. Hwang, J. Kim, and D.-K. Jeong, "Reduction of pump current mismatch in charge-pump PLL," Electronics Letters, vol. 45, no. 3, pp. 135–136, Feb. 2009, doi: 10.1049/el:20092727.
[22] Y. -W. Chen, Y. -H. Yu and Y. -J. E. Chen, "A 0.18-μm CMOS Dual-Band Frequency Synthesizer With Spurs Reduction Calibration," in IEEE Microwave and Wireless Components Letters, vol. 23, no. 10, pp. 551-553, Oct. 2013, doi: 10.1109/LMWC.2013.2279113.
[23] T. -H. Lin, C. -L. Ti and Y. -H. Liu, "Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional-N PLLs," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 5, pp. 877-885, May 2009, doi: 10.1109/TCSI.2009.2016180.
[24] V. Mazzaro and M. P. Kennedy, "Folded Noise Prediction in Nonlinear Fractional-N Frequency Synthesizers," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 10, pp. 4038-4048, Oct. 2021, doi: 10.1109/TCSI.2021.3104275.
[25] Dekking, F. M., Kraaikamp, C., Lopuhaä, H. P., & Meester, L. E. (2005). A Modern Introduction to Probability and Statistics: Understanding why and how (Vol. 488). London: springer.
[26] 劉深淵, 楊清淵. 鎖相迴路. 滄海, 2006.
[27] T. -H. Lin, C. -L. Ti and Y. -H. Liu, "Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional-N PLLs," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 5, pp. 877-885, May 2009, doi: 10.1109/TCSI.2009.2016180.
[28] L. D. Oinam and A. Singh, "Design Approach and Performance Analysis of Type I, Type II, and Type III PLL," 2023 7th International Conference on Computer Applications in Electrical Engineering-Recent Advances (CERA), Roorkee, India, 2023, pp. 1-6, doi: 10.1109/CERA59325.2023.10455725.
[29] B. Razavi, "The Transimpedance Amplifier [A Circuit for All Seasons]," in IEEE Solid-State Circuits Magazine, vol. 11, no. 1, pp. 10-97, Winter 2019, doi: 10.1109/MSSC.2018.2881860.
[30] B. Razavi, "The z-Transform for Analog Designers [The Analog Mind]," in IEEE Solid-State Circuits Magazine, vol. 12, no. 3, pp. 8-14, Summer 2020, doi: 10.1109/MSSC.2020.3002137.
[31] X. Chen, J. Winkelhake, M. -D. Wei and R. Negra, "Low-Power Class-C VCO in SiGe BiCMOS With Varactor Embedded in Cross-Feedback Path for Tuning Range Enhancement," in IEEE Transactions on Microwave Theory and Techniques, vol. 73, no. 10, pp. 7548-7557, Oct. 2025, doi: 10.1109/TMTT.2025.3567766.
[32] C. -W. Yao et al., "A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration," in IEEE Journal of Solid-State Circuits, vol. 52, no. 12, pp. 3446-3457, Dec. 2017, doi: 10.1109/JSSC.2017.2742518.
[33] A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly and P. K. Hanumolu, "A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider," in IEEE Journal of Solid-State Circuits, vol. 51, no. 8, pp. 1771-1784, Aug. 2016, doi: 10.1109/JSSC.2016.2557807.
[34] W. -S. Chang, P. -C. Huang and T. -C. Lee, "A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector," in IEEE Journal of Solid-State Circuits, vol. 49, no. 12, pp. 2964-2975, Dec. 2014, doi: 10.1109/JSSC.2014.2359670.
[35] M. Liu, R. Ma, S. Liu, Z. Ding, P. Zhang and Z. Zhu, "A 5-GHz Low-Power Low-Noise Integer-N Digital Subsampling PLL With SAR ADC PD," in IEEE Transactions on Microwave Theory and Techniques, vol. 66, no. 9, pp. 4078-4087, Sept. 2018, doi: 10.1109/TMTT.2018.2840987.
[36] B. Razavi, "The Design of An LDO Regulator [The Analog Mind]," in IEEE Solid-State Circuits Magazine, vol. 14, no. 2, pp. 7-17, Spring 2022, doi: 10.1109/MSSC.2022.3167308.
[37] W. Wu, "Digital-to-Time Converter and Its Application to Fractional-N Frequency Synthesis: Circuits from a Systems Perspective," in IEEE Solid-State Circuits Magazine, vol. 17, no. 1, pp. 52-68, winter 2025, doi: 10.1109/MSSC.2024.3496833.