在現代晶片設計中，功率消耗已成為一嚴重的問題。幾個技術已經被提出用來減少功率消耗。由於脈波驅動閘比起正反器有較少的電容值，在那些技術當中的脈波驅動閘技術使用脈波驅動閘取代正反器。此外，最近的脈波時脈閘控制技術也已經被提出，是使用在脈波驅動閘電路的時脈閘控制技術以降低功率消耗。然而，脈波時脈閘控制技術當中的時脈閘控制元件也許會違反時序條件，因而導致脈波時脈閘控制技術功能異常，進而造成電路上嚴重的錯誤。因此，本篇論文提出一個演算法解決脈波時脈閘控制技術上的時序問題。我們使用線性搜尋演算法決定脈波產生器的位置並滿足時序限制，並且使用最小成本最大流的網路流演算法總體地決定脈波驅動閘電路的時鐘樹拓樸。實驗結果顯示我們提出的演算法相對於最先進演算法在考慮時序條件下，可以更有效的降低功率消耗。

Low power design is a crucial issue in modern circuit design. Several techniques have been developed to save power consumption. Of those techniques, the pulsed-latch technologies replace flip-flops with pulsed latches due to smaller capacitance of the latter. Additionally, the clock gating of pulsed-latch circuit, which is called pulser gating, has been developed recently to further reduce power consumption. However, pulser gating may incur a timing violation in the clock gating cell, making it impossible to operate the pulser gating correctly, and ultimately causing a fatal error in the circuits. Therefore, this work propose an algorithm to resolve the problem of pulser gating and timing constraints simultaneously. We use a line-search algorithm to determine gate location to satisfy the timing constraint and apply the minimum-cost maximum-flow network to globally determine the clock-tree topology of pulsed-latch circuits. Experimental results indicate that the proposed algorithm can reduce power consumption with timing constraint e ectively compared to state-of-the-art proposed.

[1] W. Hou, D. Liu, and P.-H. Ho, "Automatic register banking for low-power clock trees," in Proc. Intl. Symposium on Quality of Electronic Design, pp. 647-652, 2009.
[2] R. S. Shelar, "An efficient clustering algorithm for low power clock tree synthesis," in Proc. Intl. Symposium on Physical Design, pp. 181-188, 2007.
[3] S. Shibatani and A. Li, "Pulse-latch approach reduces dynamic power," In the Electronic Engineering times (EE times), 2006.
[4] H.T. Lin. "Pulsed-latch-based clock tree migration for dynamic power reduction," In the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 39-44, 2011
[5] Y. L. Chuang, S. Kim, Y. Shin, and Y. W. Chang, "Pulsed-latch-aware placement for timing-integrity optimization," In the ACM/IEEE Design Automation Conference (DAC), pp. 280-285, 2010.
[6] S. Kim, I. Han, S. Paik, and Y. Shin, "Pulser Gating: A Clock Gating of Pulsed-Latch Circuits," In the ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp. 190-195, 2011.
[7] S.K. Teng and N. Soin, "Regional clock gate splitting algorithm for clock tree synthesis," In the IEEE International Conference on Semiconductor Electronics (ICSE), pp. 131-134, 2010.
[8] G.E. Tellez, A. Farrahi, and M. Sarrafzadeh "Activity-Driven Clock Design for Lower Power Circuits," In the ACM/IEEE The International Conference on Computer-Aided Design (ICCAD), pp. 62-65, 1995
[9] J. Oh and M. Pedram "Gated Clock Routing for Low-Power Microprocessor Design," In the IEEE Transactions on Computer-Aided Design (TCAD), pp. 715-722, 2001
[10] Amir H. Farrahi, C. Chen, A. Srivastava, G. Tellez, and M. Sarrafzadeh "Activity-Driven Clock Design," In the IEEE Transactions on Computer-Aided Design (TCAD), pp. 705-714, 2001
[11] C. Chen, C. Kang and M. Sarrafzadeh "Activity-Sensitive Clock Tree Construction for Low Power," In the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 279-282, 2002
[12] C. Kang and C. Chen "Activity-Sensitive Clock Design for Low Power Consumption," In the IEEE Canadian Journal of Electrical and Computer Engineering (CJECE), pp. 221-226, 2007
[13] H. C. Li, M. C. Chen, and K. M. Ho, "System and method of replacing flip-flops with pulsed latches in circuit designs," U. S. Patent, no.7694242B1, 2010.
[14] H. Partovi, R. Burd, U. Salim, F. Weber, L. DiGregorio, and D. Draper, "Flow-through latch and edge-triggered flip-flop hybrid elements," in Proc. Int. Solid-State Circuits Conf., pp. 138-139, 1996.
[15] A. Venkatraman, R. Garg, and S. P. Khatri, "A robust, fast pulsed flip-flop design," in Proc. Great Lakes Symp. VLSI, pp. 119-122, 2008.
[16] Q. Wu, M. Pedram, and X. Wu, "Clock-gating and its application to low power design of sequential circuits," IEEE Trans. on Circuits and Systems I, vol. 47, no. 3, pp. 415-420, 2000.
[17] B. Cherkasssky, "Efficient Algorithms for the Maximum Flow Problem," Math. Methods Solution Economical Problems, vol. 7, pp. 117-126, 1977.
[18] http://cad contest.cs.nctu.edu.tw/cad11/index.htm
[19] ISPD'10 CNS Contest, http://www.ispd.cc/contests/10/ispd10cns.html