本篇論文主要的目的是研究深次微米元件之熱載子可靠度。將藉由與業界的合作，取得現今產業界先進的0.18μm及0.15μm製程技術元件，進一步探討元件縮小化對元件可靠度的影響。
隨著製程技術的演進，元件縮小化的優點，儘管諸如元件密集度上升、成本的下降及元件擁有較大的驅動電流等。但隨之而來的超薄氧化層所造成的漏電流效應及短通道效應，卻在可靠度方面產生嚴重的問題。以0.18μm及0.15μm製程技術元件為例，通道長度已縮小至(0.18μm及0.15μm)，而閘極氧化層也在20～50Å左右，此時元件的熱載子效應是否仍符合長通道元件所預期一般，及超薄氧化層所造成的漏電流效應，對元件可靠度的影響，都是值得注意的問題。
本篇論文將分四大章節討論。第一章將簡要的介紹何謂熱載子效應。一些關於熱載子效應的相關基本資料及概述將在此章節中一一介紹。第二章主要是探討nMOSFET深次微米元件熱載子效應的影響。研究發現，當製程技術演進至0.18微米，元件受到熱載子效應的影響而將會有新的物理現象產生。我們發現，元件最嚴重退化的程度不再是固定在量測Vd 值為0.1V而是Vd,p ＞ 0.1V。且當元件操作在較高的溫度和外加基板偏壓時，此現象會更趨嚴重。在本篇論文中，我們將提出一個簡易的模型來解釋此現象。模型的理論簡述如下。隨著量測Vd值的增加，速度飽和區(velocity saturation region)所造成的遮蔽效應(saturation region effect)和較少的帶電介面陷阱(charged interface states)將減緩元件退化程度。然而汲極區(drain region)通道內載子的數量卻會隨著量測Vd值的增加而減少，導致退化程度更趨嚴重。所以Vd,p ＞ 0.1V的現象便是由這兩種機制彼此間的相抗衡所造成的。
第三章是探討何種機制將會造成pMOSFET在較高閘極偏壓情況下加速退化的現象。經由實驗結果的驗證，我們發現，對PMOS元件而言，當元件偏壓在較高的閘極電壓時，超薄氧化層將導致閘極電子滲透到通道，與通道中的電洞產生復和(即所謂的歐傑復和效應)，而電子電洞對復和所產生的能量，將導致更嚴重的熱載子效應。研究顯示，當元件操作在較高溫度及較低的偏壓情況時，此效應會更加嚴重。此外，F-N穿遂電流對高偏壓的閘極元件可靠度有一定程度的影響。研究發現，F-N穿遂電流對元件可靠度影響的嚴重程度受穿遂電流中電洞流成分多寡的影響。所以造成其對pMOSFET所造成的影響更勝於nMOSFET。
而在第四章中，我們將進一步的提出對本論文一些有待改進的地方。諸如：在第二章中可利用模擬軟體來增加模型準確度的方法和建議，或經由量測0.15μm製程技術元件，進一步確認模型的準確性。而對於第三章的部分，我們也將針對實驗上的缺點進行完整性的探討。

In this study, the effects of hot-carrier induced drain current degradation and gate leakage current induced by ultra-thin gate oxide on 0.18μm and 0.15μm CMOS devices will be investigated.
In the first chapter, the background of hot-carrier effects will be discussed. Results show that in deep submicron device, the worst case of hot-carrier induced drain current degradation is characterized at drain voltage higher than 0.1V which was well known as the worst case condition in long channel device. The worst case of characterized Vd was found to lager at higher temperature and substrate bias. A simplified model was presented to explain this new observation. Results show that the lowering of quasi-fermi level and the effect of the velocity saturation region (DL) contribute to the monotonically decrease ΔID/ID (%) as a function of measured VD. However, Qinv near the drain side also decreases since Vc increases. This mechanism results in the increase in DId/Id. Hence, the value of the worst case of characterized Vd is determined by this two competing mechanisms.
In the third chapter, enhanced hot-carrier induced Id degradation under high gate voltage stress was observed in pMOSFETs. Some mechanisms which may contribute to this phenomenon are discussed here。Results show that (I) F-N tunneling-current stress has finite effect on enhanced high gate voltage stress although gate oxide electric field as high as above 15MV/cm was applied. Anode hole injection model was adopted to explain the server F-N tunneling effect on pMOSFET than on nMOSFET. The hole component of the injected F-N tunneling-current was found to the dominant mechanism. (II) Electron tunneling from the gate due to ultra-thin gate oxide and Auger recombination assisted hot hole energy gain process were found to contribute to this phenomenon. Besides, this enhancement in Id degradation is more significant under high temperatures or lower supply voltages.
Finally, in the last chapter, future work is discussed.

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