本論文研究應用於DS-UWB接收機之直接降頻式前端RFICs，包括兩個應用於UWB低頻段之寬頻雙平衡式混波器、一個寬頻發射放大器以及一個差動式寬頻前端晶片。其中之寬頻前端晶片又包括寬頻差動低雜訊放大器及寬頻雙平衡式混波器。晶片製作均使用TSMC 0.18-μm 1P6M CMOS製程，晶片量測上除了發射放大器使用on-wafer方式量測之外，其餘皆採用打鎊線至PCB測試板上進行。
3-5-GHz寬頻雙平衡式混波器中，第一顆使用電荷注入式之技巧增加混波器的線性度，量測結果顯示轉換增益為3.8-5.6 dB，IIP3為-7.8- -4 dBm，IP1dB為-18- -11.9 dBm，雜訊指數為11.1-21.2 dB，LO-RF、LO-IF、RF-IF隔離度皆大於23 dB。第二顆則針對寬頻雙平衡式混波器的輸出端緩衝器做變化，改以主動平衡器取代，量測結果顯示轉換增益為3.5-6.3 dB，IIP3為-9.6- -5 dBm，IP1dB為-13.9- -9 dBm，雜訊指數為10.3-18 dB，LO-RF、LO-IF、RF-IF隔離度皆大於22 dB。
3-5-GHz共閘級輸入式寬頻發射放大器，輸入採Butterworth濾波器方式做寬頻匹配，模擬結果顯示增益為11.9-12.8 dB，OP1dB為-1.3 dBm，OIP3為8.7 dBm，隔離度為35-43 dB，PAE為3.04%，量測結果顯示增益為2-7.15 dB，隔離度大於30 dB，由於製程製作上晶片的誤差，OIP3、OP1dB與PAE則無法量測與計算。
3-5-GHz差動式寬頻前端晶片，僅混波器的部份有動作而低雜訊放大器則無法作用。差動式寬頻前端晶片模擬結果顯示增益為23.7-25.8 dB，IIP3為-14.3- -16.6 dBm，IP1dB為-26.2- -25 dBm，隔離度皆大於40 dB。
附錄中也收錄了吾人前期所設計一3-5-GHz CMOS UWB寬頻負回授混波器，CMOS混波器雜訊模型介紹，及混合式S參數介紹。

This thesis presents the research on front-end RFICs of direct-conversion for DS-UWB receiver, including of two broad-band double-balanced mixers, a broad-band transmitting amplifier and a broad-band front-end chip all applied at UWB low band. The front-end chip includes a broad-band differential LNA and a broad-band double-balanced mixer. The chips are fabricated by a TSMC standard 0.18-μm CMOS process. The circuit measurements are performed by using a FR-4 PCB test fixture except for the transmitting amplifier chip.
The first mixer chip uses charge-injection method to improve its linearity. The measurement results exhibit a conversion gain of 3.8-5.6 dB, IIP3 of-7.8- -4 dBm, IP1dB of -18- -11.9 dBm, noise figure of 11.1-21.2 dB, and LO-RF, LO-IF, RF-IF isolation more than 23 dB. The second mixer chip substitutes the buffers of broad-band double-balanced mixer with an active balun. The measurement results exhibit a conversion gain of 3.5-6.3 dB, IIP3 of -9.6- -5 dBm, IP1dB of -13.9- -9 dBm, noise figure of 10.3-18 dB, and LO-RF, LO-IF, RF-IF isolation more than 22 dB.
The chip of a 3-5-GHz common-gate transmitting amplifier uses a Butterworth filter for input broad-band matching. The simulation results show a gain of 11.9-12.8 dB , OP1dB of -1.3 dBm(@4.1 GHz), OIP3 of 8.7 dBm(@4.1 GHz), isolation of 35-43 dB, and PAE of 3.04%. The measurement data shows a gain of 2-7.15 dB, isolation more than 30 dB. Due to some errors made by process, the parameters such as OIP3, OP1dB and PAE cannot be measured and calculated.
The measurement of the 3-5-GHz differential broad-band front-end circuits show that only mixer can work and LNA cannot work. The simulation results exhibit a gain of 23.7-25.8 dB, IIP3 of -14.3- -16.6 dBm, IP1dB of -26.2- -25 dBm, and isolation more than 40 dB.
The appendix also includes a 3-5-GHz UWB CMOS mixer using feedback method I studied and designed at early days, the introduction in noise model of a mixer, and the mixed-mode S-parameter.

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