在數位訊號或影像處理的領域中，非線性中值濾波器已廣泛的被使用來去除脈衝雜訊，且可以有效地保有原始訊號的特性。此外，對於許多即時處理的影像應用來說，去除雜訊的中值濾波器硬體實現是不可或缺的。
在本論文中，我們針對一維中值濾波器提出兩個有效的硬體架構，其電路架構皆採用字級濾波方式設計。一般而言，對於連續樣本的中值取得，是透過窗口中樣本的排序，然後選擇中間值作為輸出。當窗口滿的時候，則必須刪除在窗口中一個最舊的值，然後再插入一個新進值於適當的位置上。在本文中，我們會先介紹的是實現一個面積有效率的硬體架構，此新的硬體架構是基於[11]所提出的，以提高產出及降低成本為目標。在此架構的設計上，我們提一新的控制電路，把原本需要兩個週期才能完成的樣本刪除與插入的動作，在我們的架構中只需要一個時脈週期即可完成運算，此外，我們亦針對控制電路的設計上以邏輯最佳化的化簡方法來實現，大大的改善整體硬體成本使用。經由實驗的結果顯示，與其它文獻電路架構相比之下，此電路僅需要較低的硬體成本及一個週期即可完成運算。
然後，在本論文中的第二個架構是實現一低功率的中值濾波器硬體電路。在基於排序網路的中值濾波器架構上，其運算是對於輸入的樣本進行排序然後在選擇中間值，在這些架構上，當有新的樣本值進入時，有些被儲存在窗口的樣本會依據它們的值可能會被左移或右移至其他窗口，對於一些需要較大樣本寬度的應用來說，在電路上可能需要更多的訊號傳遞，而造成更多的動態功率消耗，為了解決上述的問題，我們在電路架構設計上採用了記號環的概念，使儲存在窗口中的樣本值不需要進行移動排序，當有新的樣本進入窗口時，只需要更新每個樣本的排名，這樣一來，就可有效地減少電路中訊號的傳遞，藉此達到節省功率消耗的效果。實驗結果顯示我們和其它文獻電路架構相比之下，此電路的功率消耗為最低，但需要一些額外面積的代價。
此論文中，所有的硬體架構之實現是使用Verilog硬體描述語言，電路合成是利用Synopsys Design Vision以及TSMC的標準元件庫，電路的佈局與繞線是採用Synopsys IC Compiler，接著透過Synopsys Star-RCXT提取寄生參數，最後在採用Synopsys PrimeTime PX量測電路佈局後模擬的功率消耗。依據合成結果與功率消耗量測，我們所提出的兩個電路架構設計上分別在硬體成本與低功率消耗上具有極佳的競爭力。

A median filter is a nonlinear filter widely used in digital signal and image processing for filtering out impulse noise while preserving the crucial properties of the underlying signal. Many practical real-time image applications typically require the hardware imple-mentation of a median filter.
This dissertation presents two VLSI architectures for a one-dimensional (1-D) median filter. Word-level samples were sequentially processed by word. The median of a set of samples is often computed by sorting the samples and then selecting the middle value. When a sample enters the window, the oldest sample is removed, and the new sample is inserted in an appropriate position. For the first architecture proposed in this dissertation, the concept in [11] was extended by proposing a new word-level 1-D filter architecture. For achieving the objective of high-throughput and area-efficient VLSI implementation of the proposed method, the processes of deleting and inserting samples were combined into one clock cy-cle (a new control circuit is proposed for governing these two operations). The combina-tional control unit was then implemented using a logic optimization method. The proposed design was compared with that of a previous study, and the results indicated that the pro-posed design demonstrated superior area efficiency.
The median of a set of samples in the word-level sorting network is conventionally computed by first sorting the input samples and then selecting the middle value. In these conventional methods, when a new sample enters the window, some of the stored samples must be shifted left or right depending on their values. For some applications that require a larger sample width, more signal transitions are required in the circuit (i.e., more dynamic power is consumed). For solving this problem, the second architecture proposed in this disser-tation, a low power consumption architecture is proposed for designing of a 1D median filter, which was implemented by keeping the stored samples in the window immobile by using a token ring. Only the rank of each sample must be updated in each new cycle when an input sample enters the window. The power consumption is reduced by decreasing the number of signal transitions in the circuit. The experimental results indicated that the power con-sumption for median filters in practical use was successfully reduced at the expense of some area overhead.
The VLSI architectures of the proposed design were implemented by using Verilog HDL and synthesized by SYNOPSYS Design Vision with the TSMC cell library. Concern-ing the chip layout, Synopsys IC Compiler was adopted for automatic placement and rout-ing (APR). Finally, Synopsys Star-RCXT was adopted for parasitic extraction, and the total power consumption obtained from the post-layout simulation was measured using Synop-sys PrimeTime PX. The synthesis results and total power consumption showed that the proposed designs have the advantages of low cost and low power, separately.

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