自從1964年摩爾定律提出半導體技術的發展一直在蓬勃進步，元件尺寸的微縮以及其面臨到的種種問題是個沒有終點的挑戰，尤其是元件尺寸微縮後所帶來的短通道效應、雜訊干擾以及元件老化一直是我們所關注的議題，其中由於小面積奈米元件的電性對單顆缺陷導致的雜訊更加敏感，因此對於單顆缺陷導致的隨機電報雜訊(random telegraph noise)的關注也大幅提升。
此研究中是利用TCAD模擬軟體建構出符合 International Roadmap for Devices and Systems (IRDS) 規定的7nm尺寸 FinFET元件，並在元件通道的側壁(sidewall)上透過指定缺陷位置的方式模擬出缺陷所在位置對RTN振幅的影響。
此研究中分別以指定側壁上不同高度位置以及不同長度位置的方式進行比較，透過此研究可以知道缺陷位在側壁上哪個位置對元件的雜訊影響最深。隨後，我們也延伸至模擬兩顆缺陷同樣以指定位置的方式進行RTN振幅的比較，我們分別指定兩顆缺陷在不同高度位置、不同長度位置以及分別在兩個側壁上不同位置所造成的RTN振幅比較。最後是增加陷阱顆數到9顆進行模擬，比較多顆缺陷在集中與分散於側壁中心位置上以及沿著通道高度不同位置與沿著通道長度不同位置上元件的RTN振幅大小，期望透過增加缺陷顆數與其分布位置可以得知其對RTN的影響。

Since the proposal of Moore's Law in 1964, the development of semiconductor technology has been progressing rapidly. The continued miniaturization of device sizes and the various challenges faced are ongoing, especially with the challenges of scaling downsizes. Issues such as short-channel effects, performance enhancements, noise interference, and device aging have always been our concerns. Particularly, with the miniaturization of nanodevices, the small area makes them more sensitive to the noise caused by individual traps, thus increasing attention to the random telegraph noise (RTN).
In this study, we utilized TCAD simulation software to construct 7nm FinFET devices that comply with IRDS regulations. By simulating the impact of trap positions on RTN amplitude on the sidewalls of the device channels, we compared the effects of different height positions and different length positions on the sidewalls. Through this study, we aim to determine which position of traps on the sidewalls has the most significant impact on device noise. Subsequently, we extended our simulations to compare RTN amplitudes using two traps placed at specified positions, including different height positions, different length positions, and positions on different sidewalls. Finally, we increased the number of traps to 9 for simulation and compared the RTN amplitudes of devices with multiple traps concentrated or dispersed at the center of the sidewalls, as well as at different positions along the channel height and length. Through increasing the number of traps and varying their distribution positions, we aim to understand their impact on RTN.

[1] Neamen, “Semiconductor Physics and Devices: Basic Principles 4/e,” 2012.
[2] I. Present, "Cramming more components onto integrated circuits," Readings in computer architecture, vol. 56, 2000.
[3] K. J. Kuhn, " Potential future generation nanoscale MOS device: Trigate (TG) or Double Gate (DG) FinFETs," in 3rd International Nanoelectronics Conference (INEC), 2010, IEEE.
[4] Lorenzo Mari, " A Comparison of FinFET Configurations," 2020.
[5] Synopsys TCAD of TCAD solution
[6] Mehedi, M, " Characterisation and modelling of Random Telegraph Noise in nanometre devices," Doctoral thesis, Liverpool John Moores University, pp.8-9, 2022.
[7] K. S. Ralls et al., “Discrete resistance switching in sub-micrometer inversion layers: individual interface traps and low-frequency (1/f) noise”, Phys. Rev. Lett. 52 228–31, 1984.
[8] J. Martín-Martinez et al., "Statistical characterization and modeling of random telegraph noise effects in 65nm SRAMs cells," IEEE 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), pp. 1-4, 2017
[9] Azrif Bin Manut, “Experimental Characterization of Random Telegraph Noise and Hot Carrier Aging of Nano-scale MOSFETs”, Degree of Doctor of Philosophy, University of Liverpool John Moores, 2020.
[10] N. Tega, “Study on Impact of Random Telegraph Noise on Scaled MOSFETs”, Degree of Doctor of Philosophy, University of Tsukuba, 2014.
[11] Vikas Velayudhan., "TCAD Study of Interface Traps-related Variability in Ultra-scaled MOSFETs" Degree of Philosophy in Electrical Engineering and Computer Sciences University of California at Berkeley, March 2008.
[12] Mohan Vamsi Dunga., "Nanoscale CMOS Modeling," Electrical Engineering University of Autonoma de Barcelona, September 2016.
[13] K. K. Hung, et al., "A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors." IEEE Transactions on Electron Devices 37.3 (1990): 654-665
[14] Michael Geiger et al., "Quantitative Analysis of the Density of Trap States in Semiconductors by Electrical Transport Measurements on Low-Voltage Field-Effect Transistors," Vol. 10, Iss. 4, October 2018.
[15] M. Lax et al., “Cascade capture of electrons in solids,” Phys. Rev., vol. 119, no. 5, pp.1502-1523, Sep. 1960.
[16] Synopsys. (March 2022). Sentaurus Device UserGuide.
[17] .K. Kobayashi, et al., "Random Telegraph Noise Under Switching Operation." Noise in Nanoscale Semiconductor Devices”, pp. 285-333, Springer, Cham, 2020.
[18] James Brown, et al., "Random-telegraph-noise-enabled true random number generator for hardware security", Scientific Reports , 2020.
[19] Yun Ye, Chi-Chao Wang, Yu Cao., " Simulation of Random Telegraph Noise with 2-Stage Equivalent Circuit", Department of Electrical Engineering, Arizona State University, 2010: IEEE.
[20] S. Machlup, “Noise in semiconductors: spectrum of a two-parameter random signal,” J. Appl. Phys., vol. 25, pp. 341-343, 1954.
[21] Synopsys. (March 2016). Sentaurus Editor UserGuide.
[22] ITRS Publication. (May, 2018) ITRS_More Moore.
[23] Synopsys. (March 2016). Advanced Calibration for Device Simulation User Guide.