在本篇論文中，我們主要探討的元件為高電壓金氧半場效電晶體(HV- MOSFETs)，其中針對不同的Si recess深度對於熱載子可靠度方面的探討。在本篇論文裡，我們有三種不同Si recess 深度的元件，最深到最淺的範圍約為15奈米。
首先，描述高電壓金氧半場效電晶體的結構、優缺點以及應用的領域，接著介紹熱載子效應的基本原理以及降低熱載子效應的方法。
之後介紹本論文中的量測手法及偏壓條件的設定，並且說明Si recess結構形成的原因。在元件基本電特性的方面，我們將會呈現ID-VG、ID-VD以及ISUB-VG的量測結果。
本文研究之主要內容為基板電流對於熱載子退化量大小的研究。根據我們實驗量測的結果意外的發現，這種帶有Si recess結構的元件有著異常的熱載子退化。一般來說，基板電流越大，元件的熱載子退化量也應該要越大。但我們量測的退化趨勢，卻是基板電流越大，元件的熱載子退化卻越小。
針對這個異常的退化，我們透過實驗數據的分析以及電腦輔助模擬軟體(TCAD)，可以發現造成元件的基板電流較大的原因是它的內部電場 (electric field)和衝擊游離化率 (impact ionization rate)都較大。但造成熱載子退化量較小的方面我們提出了三種原因來解釋這個異常現象。第一有可能是較深的Si recess 深度，因為過度蝕刻的影響造成原本元件spacer下方產生較多的缺陷才會造成退化量異常的變大。其二，是因為結構上的差異造成這異常的退化。第三，我們用電腦輔助模擬軟體，模擬不同Si recess 深度元件的電流路徑分佈，可以發現較深元件的電流路徑相較於較淺的元件還要流的更貼近於表面(Si/SiO2)，因此它受缺陷的影響較大，才導致它的退化量異常的上升。根據我們的量測與模擬結果，可以發現Si recess對於元件的基本電特性影響不大，但在熱載子可靠度方面卻是不容小覷的。因為Si recess 深度增加，對元件的退化量是上升的。因此，在元件的製程中想辦法降低Si recess 結構的產生是不可避免的問題。

In this thesis, we investigated devices is High Voltage MOSFETs (HV-MOSFETs), and analysis hot carrier reliability for different Si recess depth. In our study, we have HV-MOSFETs with three different Si recess depth. The deepest to the shallowest range is about 15 nm.
First, we introduced the structure of HV-MOSFETs, its advantage and disadvantage. Moreover, hot carrier effect mechanism and reduce hot carrier effect methods were be introduced.
Then we introduced the measurement method and the setting of bias condition in this thesis, and explained the formation reason of Si recess structure. We will present the measurement results for ID-VG, ID-VD and ISUB-VG in terms of the basic electrical characteristics of the HV-MOSFETs.
The main contents of this thesis are the study of substrate current for the amount of hot carrier degradation. Based on the unexpected results of our experimental measurements, this device with a Si recess structure has an abnormal hot carrier degradation. In general, the larger substrate current, the device hot carrier degradation should also be larger. However, we measured the degradation trend is that the larger substrate current induced hot carrier degradation is smaller.
For the abnormal degradation, we analysis of experimental data and computer-aided simulation (TCAD) software, we can find that the substrate current caused by the larger part of the reason is its internal electric field and impact ionization rate is larger.
However, we have purposed three reasons to explain this abnormal phenomenon. First, a deeper Si recess depth is caused by excessive etching induced more defects where below spacer. Secondly, the topology difference induced this phenomenon. Thirdly, the linear region drain current of a deeper Si recess depth is closer to interface (Si/SiO2) than shallower Si recess depth. Therefore, the current path of a deeper Si recess device is affected by interface state more than shallower Si recess device. So a deeper Si recess device has more degradation than shallower Si recess device.
According to our measurement data and simulation results, it can be found that Si recess has little effect on the basic electrical performance of devices, but this structure is not ignore issue in hot carrier reliability. Because the depth of Si recess increases, the amount of hot carrier degradation of the device is increases. Therefore, it is an important challenge to reduce the production of Si recess structure in the process of device.

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