離散小波轉換被廣泛地應用在信號分析、信號壓縮、圖形識別、生物醫學及數值分析等不同領域，但近年來電腦科學家研究指出，小波轉換處理一維資料資料時有很好的效果，但對高維度的資料處理效果則不是很好。為了補強小波轉換的弱點，科學家們提出新的轉換，像是ridgelet轉換與curvelet轉換。由於這兩種轉換的運算甚為複雜，因此需要考量硬體實現以符合即時應用的需求。
Radon轉換為這兩種新轉換的基礎運算，本論文即是以此為研究目標。我們研究Radon轉換的演算法內容，進而規劃出兩種不同導向的參數化(parameterized)硬體架構設計：一為低成本架構，另一則為高速架構。兩種架構皆以Verilog HDL完成正反轉換的電路設計。為了因應目前的SOC(system on chip)時代，我們更設計了一個搭配的IP產生器軟體平台，讓使用者可以透過輔助軟體的幫忙，選擇自己所需硬體電路的類型，可選擇的參數包含：硬體架構（低成本／高速）、轉換型態（正／反）、精確度（低／中／高）、處理方塊大小（3／5／7／11／13），以及其他附加檔案的選擇。使用者可依自己需求勾選相對應的參數後，由IP產生器會自動輸出相對應Verilog-styled電路，方便使用者將此電路整合到所需的系統中。
最後，我們使用Synopsys Design Vision軟體，搭配TSMC 0.18μm製程元件庫，將這些由Radon轉換IP產生器所產生的不同特性IP進行邏輯合成，並列出各種不同架構下所合成的硬體電路數據比較。此外，我們也使用這些不同特性的電路，針對四張不同影像作模擬，得到訊號雜訊比等比較數據，藉以評估這些不同特性電路對影像的還原效果。

Discrete wavelet transform has proven to be a useful technique for a wide range of application including signal analysis, signal compression, pattern recognition, biomedicine and numerical analysis. According to the computer scientists’ studies in recent years, wavelet transform performs well in processing one-dimension data but worse in higher dimensions. Some transformations, such as ridgelet transform and curvelet transform, are proposed recently to solve the problem of wavelet transform. However, the computation of these transforms is very complex, hence the hardware implementations of them are required.
Radon transform is the building block of these two new transforms. In this thesis, we first study the algorithm of the finite Radon transform, and then present two different hardware architectures for two different design goals: one is low-cost and the other is high-speed. Both forward and inverse transform architectures are implemented using Verilog HDL. A finite Radon transform IP generator is developed to cooperate with our Verilog code. Our Verilog code is designed with flexibility, so that users can set the values of some parameters easily, such as hardware architecture type, transform type, precision, processing block size and other additional files, through the IP generator software interface. The IP generator will generate the specific Verilog IP automatically according to how the parameters are set.
Then we synthesize the IPs generated from the IP generator by using Synopsis Design Vision and TSMC 0.18μm cell library. We list the numerical results of the different IPs after synthesis. We also simulate these IPs for four images to obtain the quality comparisons of transformation such as MSE (mean square error) and PSNR (peak signal-to-noise ratio).

[1] R. Deans, “The Radon Transform and Some of Its Applications”, John Wiley & Sons, New York, 1983)
[2] Matus, F.; Flusser, J., “Image Representation via a Finite Radon Transform”, Pattern Analysis and Machine Intelligence, IEEE Transactions on, Vol.15, pp. 996–1006, Oct. 1993
[3] Do, M.N.; Vetterli, M., “The Finite Ridgelet Transform for Image Representation”, Image Processing, IEEE Transactions on, Vol.12, pp. 16–28, Jan. 2003
[4] Rahman, C.A.; Badawy, W., “Architectures for Finite Radon Transform”, Electronics Letters, Vol.40, pp. 931–932, July. 2004
[5] Chandrasekaran, S.; Amira, A., “High Speed / Low Power Architectures for the Finite Radon Transform”, Field Programmable Logic and Applications, 2005. International Conference on, pp. 450–455, Aug. 2005
[6] Uzun, I.S.; Amira, A., “Design and FPGA Implementation of Finite Ridgelet Transform”, Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, Vol.6, pp. 5826–5829, May. 2005
[7] Do, M.N.; Vetterli, M., “Orthonormal Finite Ridgelet Transform for Image Compression”, Image Processing, 2000. Proceedings. 2000 International Conference on, Vol.2, pp. 367–370, Sept. 2000
[8] Peng Zhang; Lin Ni, “The Curvelet Transform Based on Finite Ridgelet Transform for Image Denoising”, Signal Processing, 2004. Proceedings. ICSP '04. 2004 7th International Conference on, Vol.2, pp. 978–981, Sept. 2004
[9] Xia Jun Jun; Ni Lin; Miao, Y., “A New Digital Implementation of Ridgelet Transform for Images of Dyadic Length”, Information Technology and Applications, 2005. ICITA 2005. Third International Conference on, Vol.1, pp. 613–616, July. 2005
[10] 陳培殷, “資料壓縮概論”, 滄海, 2001
[11] 鄭信源, “Verilog硬體描述語言數位電路設計實務, 第四版”, 儒林, 2005
[12] 黃英叡, 黃稚存, “Verilog硬體描述語言, 第二版”, 全華, 2005
[13] 鄭嘉賢, “高效能上提式離散小波轉換硬體架構之設計與實現”, 南台科技大學電子工程所碩士論文, 2002
[14] 黃文達, “離散小波轉換IP產生器設計”, 南台科技大學電子工程所碩士論文, 2004