隨著電晶體的尺寸微縮，為了提高元件性能，需使用較高傳輸特性的材料作為通道，鍺因為有比矽更高的電子和電洞遷移率和較低的參雜活化溫度，被視為能取代矽的候補材料。
本實驗分別利用在(100)、(110)和(111)SOI晶圓上分別磊晶(100)、(110)和(111)晶向的鍺，並討論不同晶向的鍺在電性上的差異，但製作電晶體前須先改善鍺和介電層界面品質，因為氧化鍺(GeO)有揮發性使界面產生大量缺陷讓漏電流增加,本論文先製作氧化鍺搭配不同厚度的氧化鋁(Al2O3)或二氧化鉿(HfO2)作為介電層的鍺電容器，發現使用臭氧電漿處理搭配氧化鋁作為介電層在厚度5奈米可有效抑制漏電。
運用上述結果製作不同晶向的鍺閘極環繞電晶體,發現鍺(100)的次臨界擺幅會優於(110)和(111)晶向，N和P型閘極環繞電晶體次臨界擺幅的平均分別達到81.5mV/dec和89.1mV/dec，猜測是因為鍺(100)有最快氧化速率，使得鍺與介電層介面達到較佳品質，從P/N型場效電晶體的輸出特性曲線可看出P型鍺(110)的導通電流約為(111)的2倍，而N型鍺(111)的導通電流與(100)相比有1.37倍提升。
最後製作傳輸線模型樣品分析不同晶向的金半接觸，可發現N型鍺(111)和P型鍺(110)分別有更較低的片電阻和特徵接觸電阻率，薄層電阻值分別為247.9 ohm/sq和271.4 ohm/sq，特徵接觸電阻率則為2.83 µohm-cm²和5.05 µohm-cm²，由拉曼光譜得知不同表面晶向的鍺磊晶層皆有微小的拉伸應力，其中鍺(111)有最大的0.32%拉伸應力，接著運用X 光繞射判斷晶圓晶向和磊晶品質，發現鍺(111)展現優秀的貫穿式差排密度達到6.44×107cm-2，其結果與TEM圖吻合。由上述結果得知鍺(110)較適合作為P型電晶體，鍺(111)則適合運用在N型電晶體。

As transistor sizes continue to shrink, using materials with higher transport characteristics as the channel becomes necessary to improve device performance. Germanium is a candidate material for replacing silicon due to its higher electron and hole mobility and lower dopant activation temperature.
In this study, epitaxial growth of Ge was performed on (100), (110), and (111) SOI wafers and the electrical differences of Ge with different orientations were investigated. However, before fabricating transistors, the interface quality between Ge and the dielectric layer must be improved. Germanium oxide (GeO) is volatile, generating numerous defects at the interface, resulting in increased leakage current. In this paper, Ge capacitors with different thicknesses of aluminum oxide (Al2O3) or hafnium oxide (HfO2) as the dielectric layer were fabricated. It was found that using ozone plasma treatment in combination with aluminum oxide as the dielectric layer effectively suppressed leakage current with a thickness of 5 nm.
Based on the above results, Ge gate-all-around transistors with different orientations were fabricated. It was found that the subthreshold swing of Ge(100) was better than that of (110) and (111) crystal orientations. The average subthreshold swing of N- and P-type gate-all-around transistors achieved 81.5 mV/dec and 89.1 mV/dec, respectively. This may be attributed to the faster oxidation rate of Ge(100), resulting in a better interface quality between Ge and the dielectric layer. From the output characteristics of the P/N-type field-effect transistors, it was observed that the driving current of P-type Ge(110) was approximately twice that of (111), while the driving current of N-type Ge(111) showed a 1.37 times improvement compared to (100).
Finally, TLM (Transmission Line Model) samples were fabricated to analyze the metal-semiconductor contacts with different crystal orientations. It was found that N-type Ge(111) and P-type Ge(110) exhibited lower sheet resistance and specific contact resistivity. The sheet resistance values were 247.9 ohm/sq and 271.4 ohm/sq. The specific contact resistivity values were reduced to 2.83 µohm-cm² and 5.05 µohm-cm², respectively. Additionally, Raman spectroscopy revealed that Ge epitaxial layers with different surface orientations exhibit slight tensile stress. Among them, Ge(111) has the highest tensile stress of 0.32%. Furthermore, the crystal orientation and epitaxial quality of the wafer were determined using XRD (X-ray Diffraction). It was found that Ge(111) demonstrates excellent threading dislocation density, reaching 6.44×107cm-2. The results are consistent with TEM (Transmission Electron Microscopy) images. Based on these results, it can be concluded that Ge(110) is more suitable for use in P-type transistors, while Ge(111) is better suited for N-type transistors.

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