在本篇論文中，根據基本的射頻電路及元件設計之原理，以TMSC CMOS 0.18 μm 1P6M之製程設計出具有高功率輸出、操作於5.2 GHz的高頻功率元件，並同時量測及分析其可靠度，比較不同的高頻率及高功率應力下，所造成的元件特性退化程度。設計流程的第一步是設計輸出功率為10 dBm之功率元件，並分析會造成退化的應力來源。接著再設計輸出功率達到17、20、23 dBm之功率元件，並同時比較不同的佈局架構，對於功率特性及可靠度的影響。最後根據量測及分析的結果，設計出輸出功率可達到23 dBm、工作於2.4 GHz的功率放大器。
針對輸出功率為10 dBm之功率元件，為了了解其特性及可靠度，進行兩種不同的應力分析，分別為直流高偏壓高電流之應力及負載不匹配之情況下之高頻功率應力。由比較之結果可得知，負載不匹配下，高頻功率應力所造成之元件特性退化較直流應力明顯。在不同佈局架構下的兩種元件中，皆可發現同樣的情況。另一方面，利用分散式的佈局架構，則可有效地減少高頻功率元件所造成的應力；這樣的比較結果，也發生在輸出功率為17 dBm的兩種設計元件中。在比較不同元件之退化程度之後，可以推論出熱載子效應與佈局架構及輸出功率大小有關。
為了詳細了解負載不匹配對於熱載子效應所造成的影響，針對輸出功率為17 dBm之功率元件進行量測與分析。根據等功率增益圓的量測結果，選定六個不同的負載點。在這六個不同負載情況下，固定輸入功率，量測九十分鐘後，汲極電流的退化百分比。利用基頻及階波項之”負載不匹配指數”分析，可推論出負載不匹配與熱載子效應所造成的退化程度有一定的關係。在相同的等功率增益圓下，表示其輸出功率特性是相同的，但不同的負載，卻會造成不同的退化程度；因此利用這樣的方式分析功率元件之可靠度，是相當有效且正確的。
另外一種會造成元件特性退化的原因是”閘極氧化層崩潰”。隨著CMOS製程的進步，閘極氧化層的厚度縮小，”軟式閘極氧化層崩潰”則是薄氧化層元件最常見的可靠度問題。硬式閘極氧化層是發生在氧化層較厚的元件中，因為閘極電場過高，造成氧化層崩潰，瞬間產生極大的閘極電流，是一種不可回復性的嚴重破壞。而軟式崩潰則是因為氧化層很薄，載子是以”穿隧”的方式通過氧化層，對於氧化層的破壞較輕微，但仍會使載子陷入氧化層中，或產生介面能階，因而造成元件特性的退化。這樣的情況很類似熱載子效應，在本論文中，依據量測結果，分析、比較這兩種應力對於可靠度的影響。由比較結果得知，相對於熱載子效應，軟式閘極崩潰對於元件之特性及等效通道長度有相當大的影響。當輸出功率達到元件之極限，閘極與汲極之間的電場強度達到最大值，此時軟式崩潰就會發生，使得元件之功率特性嚴重退化。由直流特性之量測結果也發現類似”通道長度調變”的情況產生。此現像說明了通道的形成受到了軟式崩潰所產生的閘極特性影響，在不同汲極電壓下，會有不同的等效通道長度。
最後一個部分則是利用上述的設計經驗，設計出適合應用於輸出功率為23 dBm之功率元件。修正電流密度及熱效應所造成的之問題，並設計出最佳化的佈局架構，使得元件在此功率輸出範圍內，仍保持較好的可靠度。利用此功率元件設計出應用於2.4 GHz 頻率範圍的功率放大器，其特性結果也證明了此應用的可行性。

The radio-frequency (RF) power cells with high output power levels were designed by TSMC CMOS 0.18 μm 1P6M process. The power performances were measured at 5.2 GHz. The reliabilities were also measured and analyzed. The degradation from different stresses were discussed and compared with physical explanations. The design of the power cells of output power level of 10 dBm was the first step in the design procedure. Following is the designs of power cells with output power of 17, 20, and 23 dBm in turn. Based on the measurement results, the power amplifier of output power level of 23 dBm for 2.4 GHz was designed with the power cell with optimum power performances and reliabilities.
The degradation from hot-carrier effect depended on input and output power levels, layout geometries, and load impedance mismatches. Two types of layout patterns were designed for the power cells of 10 and 17 dBm. The measurement results shows that the hot-carrier effect from RF reflected power by load impedance mismatch is much larger than that of DC stress at high bias voltages. The comparisons of degrees of degradation also indicate that the degradation is softened with dispersive layout structure under RF stress.
From the comparison of degradation of power cells with output power levels of 10 and 17 dBm, it is found that the output power level of studied cells dominates the degradation both in DC and RF stress. The increased current and output power were equivalent to a higher electric field and current density at the drain terminal of MOSFET, and induced more serious hot-carrier effect and then more degradation.
The detailed measurements and analyses of the load impedance mismatches are made with the power cells of output power level of 17 dBm. The influence of RF stress resulting from load impedance mismatches at the drain terminal on the device degradation has been quantified by the load mismatch factor, ML. Six different load impedances are chosen in order to study the dependence of degradation degree on the load impedance. The value of (1-ML) and the fundamental output power level dominate the amount of reflected power and the degree of degradation of drain current. The transient voltage and current swings at drain terminal also shows the same tendency.
Another reliability issue of soft oxide breakdown in high power applications is also discussed. The effects of high RF power stress on drain current and power performances have been presented. Both the DC characteristics and power performances after hot-carrier effect and soft oxide breakdown were compared. From the experimental results of DC I-V curve, the threshold voltage shifted and the slope of drain current in the saturation region became much larger which was similar to the channel length modulation of MOSFET. The point of the pinch-off extended from drain terminal toward the source terminal and then the effective channel length was reduced in the stressed cell. The model of stressed power cells after soft oxide breakdown was introduced.
Based on the measured results and performance comparisons in different layout patterns, it is observed that the geometry of the power cells with dispersive layout patterns has both better power performances and reliability. The power cells of output power of 20 and 23 dBm were designed by using the dispersive layout geometries. Otherwise, the problems of slots in the metal interconnects of current paths were solved for lower current density. The pre-match load-pull system is also used to help the measurement with smaller load impedance for power match. Finally, the power amplifier with output power level larger than 23 dBm at 2.4 GHz is designed.

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