| 研究生: |
李柏毅 Li, Bo-Yi |
|---|---|
| 論文名稱: |
多核心軟硬體整合視覺化與圖形化開發環境框架與實作 Framework of an Integrated Development Environment for Many-Core OpenRISC SW/HW System and Its GUI Based Visualization Tools |
| 指導教授: |
蘇文鈺
Su, Wen-Yu |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 資訊工程學系 Department of Computer Science and Information Engineering |
| 論文出版年: | 2015 |
| 畢業學年度: | 103 |
| 語文別: | 英文 |
| 論文頁數: | 35 |
| 中文關鍵詞: | 異質多核心 、多核心平台 |
| 外文關鍵詞: | CPU Visualization, FPGA, GUI, IDE, OpenRISC, Many-Core, SW/HW System |
| 相關次數: | 點閱:136 下載:6 |
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隨著資訊科技的進步,多核心系統已逐漸成為近代各種桌面平台與手持式裝置的主流,目前也有不少的開發商或者開放性社群持續地開發新的架構、設備,以及相關的工具。對於大多數的學生以及工程師而言,多核心系統的研究以及相關的應用程式、系統的開發是個相當大的挑戰。然而,目前卻鮮少有方便使用的多核心軟硬體系統整合開發環境支援系統開發以及多核心架構的研究。
本篇論文將建立一個適用於搭載多核心OpenRISC的FPGA開發板或模擬器之多核心軟硬體整合圖形化介面框架,並且將為有志於最新的多核心架構的學習或教學的使用者提供一套整合編輯、編譯到執行之一連貫開發流程的視覺化工具。除此之外,此工具開發了CPU Visualization視窗以觀察CPU pipeline的運作流程。在本論文中將描述本系統在各種不同使用狀況下的使用狀況,及本系統的未來發展可能及應用彈性。
Many-core systems have become the main stream for desktop platforms and even mobile devices. Not only industries, but also opening communities keep working on developing new architectures, devices and the associate tools. Studying many-core systems and developing applications and systems become very big challenges for most students and even engineers. However, there are few user friendly integrated development environments for many-core software/hardware systems which support both system development and study of many-core computer architectures.
In this thesis, a GUI based integrated development environment is presented for many-core software/hardware system, which uses FPGA board with many-core OpenRISC or a simulator. In addition, a visualization tool is provided for those who want to learn and/or teach more up-to-date many core computer architectures. It sets up a developing routine combined with editing, compiling and executing. Furthermore, the CPU visualization window is constructed to observing the stage processing of CPU pipeline. In this thesis, the proposed platform enables different use-scenarios and reveals its potential and broad usage in performance analysis, memory system design and so on.
[1] Qt Project, http://qt-project.org/
[2] Qt digia, http://qt.digia.com/
[3] OR1K::OpenCores, http://opencores.org/or1k/Main_Page
[4] Chun-Wei Lin, A Many Core OpenRISC FPGA Platform and Tools, master thesis, NCKU, 2015
[5] SPIM MIPS Simulator, http://pages.cs.wisc.edu/~larus/spim.html
[6] spim mips simulator - Browse Files at SourceForge.net, http://sourceforge.net/projects/spimsimulator/files/
[7] Kenneth Vollmar and Pete Sanderson, MARS: An Education-Oriented MIPS Assembly Language Simulator, in ACM SIGCSE Bulletin, 38:1, p. 239-243, 2006
[8] MARS MIPS simulator - Missouri State University, http://courses.missouristate.edu/kenvollmar/mars/index.htm
[9] Mats Brorsson, MipsIt: A Simulation and Development Environment Using Animation for Computer Architecture Education, in Proceedings of the 2002 workshop on Computer architecture education: Held in conjunction with the 29th International Symposium on Computer Architecture, p. 12, 2002
[10] Accessing and Installing PathSim, http://www.cs.sbu.edu/PathSim4/