本論文針對硫化銨鈍化表面處理與進行氫氣混合氣體退火，探討對高介電係數介電層(二氧化鉿、二氧化鋁)與矽鍺介面的影響。由三-五族常見的鈍化方式為發想,透過硫化銨鈍化讓表面鍺氧化物較難形成。以及，在氨電漿處理下，所形成的阻擋層的控制能力高；另一方面，進行氫氣混合氣體退火，可以修補介面缺陷。根據實驗結果，在浸泡15分鐘的硫化銨表面處理與氨電漿和高介電係數介電層的條件下，電容在進行氫氣混合氣體退火(300°C，30分鐘)後，電性上顯示有較小的遲滯現象(約138.57 mV)與等效電容厚度(1.63奈米)，且閘極漏電流在閘極電壓為-1 V時，約為8.9×10-5 A/cm2

In this thesis,we focuses on ammonium sulfide passivation surface treatment and uses hydrogen and combination gas annealing, and discusses the effect on the interface between the high-k dielectric layer (HfO2) and SiGe. Based on the common passivation methods of III-V semicondoutor, it is difficult to form GeOx on the surface through ammonium sulfide passivation. And, under the NH3 plasma treatment, due to the surface nitridation, the formed barrier layer has a high controllability; on the other hand, the metal annealing after hydrogen can repair the interface defects. According to the experimental results, under the conditions of 15 minutes of ammonium sulfide surface treatment, ammonia plasma and high-k dielectric layer, the capacitors show better electrical characteristic after metal post annealing (300°C, 30 minutes). Small hysteresis loop of ~138.57 mV and equivalent capacitance thickness (1.63 nm), and the gate leakage current is about 8.9×10-5 A/cm2 when the gate voltage is -1 V .

[1] C.D.Young, "Enabling Semiconductor Innovation and Growth-EUV lithography drives Moore's law well into the next decade," in APAC TMT Conference, Taipei, Taiwan, March 14, 2018 2018.
[2] B. S. Doyle and B. Roberds, "Methodology for control of short channel effects in MOS transistors," applications: 2001.
[3] D. Monroe, J. Hergenrother , and S.-H .Oh, "Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs," IEEE electron device letters, pp. 445-447, 2000.
[4] Robert Castellano, "Watch For EUV Lithography Equipment Pushouts, Revenue Misses For ASML,Sep. 5, 2018
[5] DBS" 2020 Investment Insights-Semiconductor Technology Development and 5 Application Trends, Jan,01, 2020.
[6] E. Bassous,F. H. Gaensslen, and V. L. Rideout"Design of ion-implanted MOSFET's with very small physical dimensions," IEEE Journal of Solid-State Circuits, vol. 9, no. 5, pp. 256-268, 1974.
[7] H.-K. Lim and J. G. Fossum, "Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET's," IEEE Transactions on electron devices, vol. 30, no. 10, pp. 1244-1251, 1983.
[8] DIETER K. SCHRODER, " SEMICONDUCTORMATERIAL AND DEVICE CHARACTERIZATION," John Wiley＆Sons，Inc.,pp.63,2005
[9] G. D. Wilk, J. Anthony, R. M. Wallaceand, "High-κ gate dielectrics: Current status and materials properties considerations," Journal of applied physics, vol. 89, no. 10, pp. 5243-5275, 2001.
[10] Junling Lu ,Jeffrey W.Elamb,and Peter CStaircd, "Atomic layer deposition—Sequential self-limiting surface reactions for advanced catalyst “bottom-up” synthesis," ScienceDirect, vol.71, no. 2, pp. 410-472, 2016.
[11] K. Yamamoto, S. Hayashi, M. Kubota, and M. Niwa, “Effect of Hf metal predeposition on the properties of sputtered HfO2/Hf stacked gate dielectrics,” Appl. Phys. Lett., vol. 81, pp. 2053-2055, 2002.
[12] M. R. Visokay, J. J. Chambers, A. L. P. Rotondaro, A. Shanware, and L. Colombo, “Application of HfSiON as a gate dielectric material,” Appl. Phys. Lett., vol. 80, pp. 3184-3185, 2002.
[13] X. Yu, C. Zhu, M. F. Li, A. Chin, M. B. Yu, A. Y. Du, and D. L. Kwong, “Mobility enhancement in TaN metal-gate MOSFETs using tantalum incorporated HfO2 gate dielectric,” IEEE Electron Device Lett., vol. 25, pp. 501-503, 2004.
[14] A. Paskaleva, A. J. Bauer, M. Lemberger, and S. Zurcher, “Different current conduction mechanisms through thin high-k HfxTiySizO films due to the varying Hf to Ti ratio,” J. Appl. Phys., vol. 95, pp. 5583-5590, 2004.
[15] C. S. Park, B. J. Cho, and D. L. Kwong, “MOS characteristics of synthesized HfAlON-HfO2 stack uaing AlN-HfO2,” IEEE Electron Device Lett., vol. 25, pp. 619-621, 2004.
[16] X. Wang, J. Liu, F. Zhu, N. Yamada, and D. L. Kwong, “A simple approach to fabrication of high-quality HfSiON gate dielectric with improved nMOSFET performances,” IEEE Trans. Electron Devices, vol. 51, pp. 1798-1804, 2004.
[17] C. S. Kang, H.-J. Cho, R. Choi, Y. H. Kim, C. Y. Kang, S. J. Rhee, C. Choi, M. S. Akbar, and J. C. Lee, “The electrical and material characterization of Hafnium oxynitride gate dielectric with TaN-gate electrode,” IEEE Trans. Electron Devices, vol. 51, pp. 220-227, 2004.
[18] D.M. Fleetwood, P.S. Winokur, R.A. Reber Jr, T.L. Meisenheimer, J.R. Schwank,M.R. Shaneyfelt, et al., Effects of oxide traps, interface traps, and “border traps” onMOS devices, J. Appl. Phys. 73 (1993) 5058–5074.
[19] D.K. Schroder, “ Electrical characterization of defects in gate dielectrics, inD.M. Fleetwood, S.T. Pantelides, R.D. Schrimpf (Eds.), Defects in MicroelectronicMaterials and Devices, CRC Press, Boca Raton, FL, ”2008, pp. 119–162.
[20] D.K. Schroder, J.A. Babcock, Negative bias temperature instability: road to cross indeep submicron semiconductor manufacturing, J. Appl. Phys. 94 (2003) 1–18.
[21] Dr. M. Tahoori, Border traps and bias-temperature instabilities in MOS devices, Microelectronics Reliability 80 (2018) 266–277 Available online 20 November 2017
[22] S. M. Sze, “Semiconductor devices, physics and technology,” John Wiley & Sons, 1985.
[23] W. Zhu, J.-P. Han, and T. P. Ma, “Mobility measurement and degradation mechanisms of MOSFETs made with ultrathin high-k dielectrics,” IEEE Trans. Electron Devices, vol. 51, no. 1, pp. 98–105, Jan. 2004.
[24] M. V. Fischetti, D. A. Neumayer, and E. A. Cartier, “Effective electron mobility in Si inversion layers in metal-oxide-semiconductor systems with a high-k insulator: The role of remote phonon scattering,” J. Appl. Phys., vol. 90, pp. 4587–4608, 2001.
[25] D. K. Schroder, and J. A. Babcock, “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing,” J. Appl. Phys., vol. 94, no. 1, pp. 1–18, 2003
[26] A. Alian,M. Heyns and G. Brammertz “Challenges for introducing Ge and III/V devices into CMOS technologies”,Apr,2012
[27] T. Weser, A. Bogen, B. Konrad, R. Schnell, C. Schug, and W. Steinmann, Photoemission surface core-level study of sulfur adsorption on Ge(100). B, 35, 8184 (1987).
[28] D.V. Lang, R. People, J.C. Bean, A.M. SergentMeasurement of the band-gap of Gexsi1-X/Si strained-layer heterostructures
[29] N. Lu, W. Bai, A. Ramirez, C. Mouli, A. Ritenour, M.L. Lee, D. Antoniadis, D.L. KwongGe diffusion in Ge metal oxide semiconductor with chemical vapor deposition HfO2 dielectricAppl.Phys.Lett., 87 (2005)
[30] Althobaiti, Mohammed “Characterization of high-κ dielectrics on Germanium” , 2016
[31] Kasra-Sardashti,Kai-TingHu,Kechao-Tang,Sangwook-Park“Sulfur passivation for the formation of Si-terminated Al2O3/SiGe(0 0 1) interfaces 0 1) interfaces”, vol.366,no.15 , pp. 455-463, 2016
[32] C. Fleischmann, M. Houssa, M. Muller, B. Beckhoff, H.G. Boyen, M. Meuris, K. Temst, A. VantommeLiquid-phase adsorption of sulfur on germanium: reaction mechanism and atomic geometry vol.117,no.15, , pp. 7451-7458, 2013
[33] S. L. Heslop, “Stability of SiGe(100) Surfaces after Ammonium Sulfide Passivation, ” vol.80,no.2,2017
[34] Mahmut S. Kavrik, Peter Ercius,“Engineering ,High‑k/SiGe Interface with ALD Oxide for Selective GeOx Reduction, ”April 2, 2019
[35] É.O’Connor, B. Brennan, V. Djara, “A systematic study of passivation (22%, 10%, 5%, or 1%) on the interface properties of the system for -type and -type epitaxial layers, ” 18 January 2011

[36] Karen M. Griffing, John Kenney, Theoretical predictions of stable negative ions: HF − , LiH − , NaH − ,03 September 2008
[37] B.Brennan, Optimisation of the ammonium sulphide (NH4)2S passivation process on In0.53Ga0.47As, 9, 15 February 2011, Pages 4082-4090
[38] Jyun-Han Li, Investigation of high-k dielectrics/SiGe interface for SiGe FinFETs fabrication, July 2019
[39] W. L. Kalb and B. Batlogg, "Calculating the trap density of states in organic field-effect transistors from experiment: A comparison of different methods," physical review B, vol. 81, no. 3, p. 035327, 2010.
[40] R. Winter, J. Ahn, P. C. McIntyre, and M. Eizenberg, "New method for determining flat-band voltage in high mobility semiconductors," Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, vol. 31, no. 3, p. 030604, 2013.
[41] W. C. Lee, C. J. Cho, J.-H. Choi, J. D. Song, C. S. Hwang, and S. K. Kim, "Correct extraction of frequency dispersion in accumulation1capacitance_inInGaAs metal-insulator-semiconductor devices," Electronic Materials Letters, vol. 12, no. 6, pp. 768-772, 2016.
[42] J. Franco et al., "SiGe channel technology: Superior reliability toward ultrathin EOT devices—Part I: NBTI," IEEE Transactions on Electron Devices, vol. 60, no. 1, pp. 396-404, 2012.
[43] K. Sardashti et al., "Nitride passivation of the interface between high-k dielectrics and SiGe," Applied Physics Letters, vol. 108, no. 1, p. 011604, 2016.
[44] R. M. Wallace,R.Degraeve, " Electrical properties of high-κ gate dielectrics: Challenges, current issues, and possible solutions," ScienceDirect, vol. 51, no. 4-6, April,2006.
[45] T. Yu, C. Jin, Y. Yang, L. Zhuge, X. Wu, and Z. Wu, "Effect of NH3 plasma treatment on the interfacial property between ultrathin HfO2 and strained Si0. 65Ge0. 35 substrate," Journal of Applied Physics, vol. 113, no. 4, p. 044105, 2013.