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研究生：	陳碩懋 Chen, Shuo-Mao
論文名稱：	互補式金氧半電晶體製程相容之先進射頻元件研製 Studies of CMOS Process Comparable Novel Devices for Advanced Radio Frequency Applications
指導教授：	方炎坤 Fang, Yean-Kuen
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 微電子工程研究所 Institute of Microelectronics
論文出版年：	2011
畢業學年度：	99
語文別：	英文
論文頁數：	97
中文關鍵詞：	互補式、金氧半電晶體、射頻
外文關鍵詞：	CMOS, Radio Frequency
相關次數：	點閱：76 下載：3
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近年來，使用於低千兆赫茲的頻率範圍的矽基射頻元件倍受注目。本論文詳細報導使用於該頻率範圍的高品質射頻電感、高性能奈米鎳矽合金之蕭特基能障二極體陣列、閘極控制之水平式雙載子接面電晶體和閘極控制之水平與垂直式雙載子接面電晶體的研究。
首先，利用0.13微米之互補式金氧半電晶體製程研製具特殊結構設計的高品質電感於矽晶片上。這些特殊結構設計包含了並聯式堆疊、條狀跨金屬間的連接，以及以上層連接訊號用途的金屬層來取代原本用於電感下方連結的訊號通道。其優點為降低電阻值、提高品質參數、簡化製程與縮小晶片面積等。實驗發現建立於四層並聯金屬、15微米的金屬線寬、5.5匝數的線圈與204乘240平方微米面積的電感，在1.8千兆赫茲的Q峰值係數可達7.06。顯示其在先進移動式通訊的應用具有較一般者為佳的潛力。
其次以最先進的45奈米互補式金氧半電晶體製程技術研製高性能奈米鎳矽合金之蕭特基能障二極體陣列。吾人以數種不同隔絕矽金化物的結構設計諸如多晶矽閘極與絕緣保護氧化層等來提高性能應用於先進射頻領域並與一般的淺溝槽隔離結構作比較。其中多晶矽閘極與絕緣保護氧化層這兩種隔絕矽金化物的結構設計不僅具有高截止頻率且製程簡單。尤以多晶矽閘極作為隔絕者的截止頻率更可高達4.6萬億赫茲。
另外，本研究以90奈米互補式金氧半電晶體製程技術實現高電流增益的閘極控制之水平式雙載子接面電晶體於射頻系統整合單晶片的應用。具0.15微米的閘極線寬的閘極控制之水平式雙載子接面電晶體可有超過2000大小的電流增益與17千兆赫茲的截止頻率和19千兆赫茲的最大震盪頻率。相較於先前發表過的水平式雙載子接面電晶體，在電流增益、截止頻率和最大震盪頻率分別改善了1000%、200%和60%。
最後，我們以先進55奈米互補式金氧半電晶體製程技術來發展擁有極低閃爍雜訊(1/f 雜訊) 的閘極控制之水平與垂直式雙載子接面電晶體陣列元件。此陣列元件並聯數種不同數目的單一個體相鄰的集極與基極可共同使用，以縮小元件面積與提升集極電流。實驗顯示以16顆0.16微米閘極線寬個體並聯組成的陣列元件，具非常低水平的1/f 雜訊並有85.7的高電流增益。相較一般的N型金氧半場效電晶體或者是垂直式矽鍺 NPN型異質接面雙載子電晶體，其1/f 雜訊至少降低了兩個等級的1/f雜訊。

Recently, Si-based RF components are widely applied in low Giga Hz frequency range. In this work, the CMOS process comparable novel Si-based RF devices such as high-Q RF inductors, high performance nanometer NiSi2-Si Schottky Barrier Diode Arrays (SBDAs), Gate-Controlled Lateral Bipolar Junction Transistors (GC-LBJTs), and Gate-Controlled Lateral-Vertical Bipolar Junction Transistors (GC-LVBJTs) are developed for the advanced low Giga Hz frequency applications.
First, the high Q on-chip inductors with some unique structures were fabricated with 0.13μm CMOS technology for the first time. The unique structures include parallel stack, line via between inter metal layers, and use of the top signal pad as the inductor under path instead of conventional bottom signal pad. These structures offer advantages of reducing resistance, high Q value, simple preparing process and small chip area. Experimental results show that the measured peak Q and peak-Q frequency can attain 7.06 and 1.8GHz , respectively for the structure with four metal layers in parallel, 15μm in metal width , 5.5 turns in wire number ,and an area of 204×240μm2. The results have a better potential for advanced mobile communication applications.
Next, high performance nanometer NiSi2-Si Schottky barrier diode arrays (SBDA) with various isolation designs, including poly Si gate (PSG) and resist protection oxide (RPO) were developed for advanced radio frequency applications. Radio frequency performances of these developed SBDAs were investigated and compared to that with the conventional shallow trench isolation. All of the SBDAs were fabricated with a foundry state-of-arts 45nm complementary metal oxide semiconductor technology. Both of PSG and RPO insulated SBDAs have higher cutoff frequency and a simpler preparing process. Specifically, the PSG insulted SBDA could achieve a cutoff frequency of up to 4.6 THz.
Then, a high current gain CMOS-compatible gate-controlled lateral BJT (GC-LBJT) was prepared with a conventional 90 nm CMOS technology for radio frequency system-on-chip (RF SoC) applications. The emitter injection efficiency and the doping profile in P-well were optimized by properly controlling source, drain and well implants. Consequently, the GC-LBJT with a gate length of 0.15μm can achieve a current gain over 2000, and 17 /19 GHz for the fT /fmax, respectively, which are 1000%, 200%, and 60% improvements in current gain, fT, and fmax, respectively as compared to the LBJT reported previously.
Finally, the very low flicker noise (1/f noise) gate-controlled lateral-vertical bipolar junction transistor array (GC-LV-BJTA) was developed with a foundry’s 55nm CMOS technology for low noise and low power RF circuit applications. The GC-LV-BJTA is formed by paralleling various number of unit cells into an array structure for sharing adjacent collectors and bases, thus minimizing the device area and enhancing collector current. Many efforts, including use of deep n-well, novel layout, optimized emitter perimeter/area ratio and negatively biased gate have been implemented to suppress the noise level and enhancement of current gain. As a result, the GC-LV-BJTA consisting 16 unit cells with 0.16µm gate length achieves a very low 1/f noise level spectrum and a high gain of 85.7. Compared to the conventional NMOS or the vertical SiGe NPN HBT, the GC-LV-BJTA has two orders lower in 1/f noise level.

Contents
Abstract (in Chinese)                                        I
Abstract (in English)                                       IⅤ
CHAPTER 1   Introduction                                   
1.1	 Background and Motivations                               1
1.2	 Overview of the Dissertation                               3
CHAPTER 2   On-Chip Parallel-Stacked Spiral Inductor 
2.1 Introduction                                             6
2.2 Structure Design Considerations                             7
2.3 Sample Preparation and Measurements                        8
2.4 Experimental Results and Discussions                       10
2.5 Summaries                                             11
CHAPTER 3   Terahertz Schottky Barrier Diodes 
3.1 Introduction                                            12
3.2 Device Design and Fabrication                             13
3.3 Experimental Results and Discussions                       15
3.4 Summaries                                             18
CHAPTER 4  Gate-Controlled Lateral Bipolar Junction Transistor 
4.1 Introduction                                            20
4.2 Device Design and Fabrication                             21
4.3 Experimental Results and Discussions                       23
4.4 Summaries                                             28
CHAPTER 5   Gate-Controlled Lateral-Vertical BJT Array      
5.1 Introduction                                            29
5.2 Device Design, Theory and Fabrication                      31
5.2.1 Theory and Design of the GC-LV-BJTA Unit Cell           31
5.2.1.1 Novel Layout                                      31
5.2.1.2 Theory                                           33
5.2.1.3 Function of the Deep n-Well                          35
5.2.2 Fabrication of Unit Cell and Array of the GC-LVBJTA       36
5.2.3 S/D Profile Engineering for the GC-LV-BJTA Unit Cell      36

5.3 Experimental Results and Discussions                       37
5.3.1 Effects of Gate Bias on Gummel Plot and Current Gain       38
5.3.2 Effect of Emitter P/A Ratio on IC/IB, β and RF Performances  39
5.3.3 1/f Noise of the GC- LV-BJTA                        40
5.3.4 Comparison to MOSFET and SiGe HBT                40
5.4 Summaries                                             41
CHAPTER 6  Conclusions and Prospect                      
Reference                                                 44

Table caption
Table 3-1 Summary of parameters including Ion, Vbd, Ileak, fTave, Rs and Cp.
Table 4-1. Comparison of beta, Va, BVceo, BVcbo, fT and fmax for the three types of NPN GC-LBJTs.
Table 5-1 Summary of the current gain and RF characteristics for split GC- LV-BJTA samples with various P/A ratios.


Figure Captions
Fig. 2-1 (a).Top view diagram of deep-submicron CMOS process compatible parallel stacked inductor.
Fig. 2-1 (b) side view of deep-submicron CMOS process compatible parallel stacked inductor.
Fig. 2-1 (c) Comparison of the “line via” and “square via”.
Fig. 2-2 The measured Q as a function of frequency for various parallel metal layers with the number of turns, radius, spacing and metal width of 5.5 turns, 30μm, 3μm, and 15μm, respectively.
Fig. 2-3 The measured inductance L as a function of frequency for various parallel metal layers with the number of turns, radius, spacing and metal width of 5.5 turns, 30μm, 3μm, and 15μm, respectively.
Fig. 2-4 Comparison of the measured Q as a function of frequency for the parallel stacked inductor (M8//M7//M6//M5, 5.5 turns and 15μm in width) using top and bottom signal pad, respectively.
Fig. 2-5 Comparison of the measured inductance as a function of frequency for the parallel stacked inductor using top and bottom signal pad, respectively.
Fig. 2-6 Comparison of the measured Q as a function of frequency for the parallel stacked (M8 only) inductor with 5.5 turns and various metal widths of 6μm, 9μm and 15μm, respectively.
Fig. 3-1 (a) A cross-sectional view of Schottky barrier diodes with poly Si type structure. 
Fig. 3-1 (b) A cross-sectional view of Schottky barrier diodes with resist protection oxide (RPO) type structure.
Fig. 3-1 (c) A cross-sectional view of Schottky barrier diodes with shallow trench isolation (STI) structure.
Fig. 3-1 (d) A typical layout design of the Schottky barrier diode array.
Fig. 3-2 Current density versus bias voltage of the three types SBDA at the same total area of 0.5×0.5×16 µm2 (16 paralleled 0.5×0.5 unit cells).
Fig. 3-3 Rs and Cp versus frequency for the three types SBD ( poly, RPO, and STI types ) at the same total area of 0.5×0.5×16 µm2(16 paralleled 0.5×0.5 unit cells).
Fig. 3-4 (a) Rs versus total area as a function of parallel number for the three types SBDA (poly, RPO, and STI types) at the same unit cell area of 0.5×0.5µm2. 
Fig. 3-4 (b) Cp versus total area as a function of parallel number for the three types SBDA (poly, RPO, and STI types) at the same unit cell area of 0.5×0.5µm2.
Fig. 3-4 (c) fT versus total area as a function of parallel number for the three types SBDA (poly, RPO, and STI types) at the same unit cell area of 0.5×0.5µm2.
Fig. 3-5 Rs, Cp and fT versus unit cell area as a function of parallel number for the STI type at the same total SBDA area of 4µm2. 
Fig. 3-6 (a) Rs versus total area as a function of unit cell area for the three types SBDA (poly, RPO, and STI types) at the same parallel number of 16.
Fig. 3-6 (b) Cp versus total area as a function of unit cell area for the three types SBDA (poly, RPO, and STI types) at the same parallel number of 16.
Fig. 3-6 (c) fT versus total area as a function of unit cell area for the three types SBDA (poly, RPO, and STI types) at the same parallel number of 16.
Fig. 4-1 (a) The SUPREM-IV.GS simulated cross sections of the NPN GC-LBJT with three types implant profile engineering: Type I of the novel structure by using gradual profile of DSC, sharp profile of DSE and lower PW implants.
Fig. 4-1(b) The SUPREM-IV.GS simulated cross sections of the NPN GC-LBJT with three types implant profile engineering: Type II of the current NMOSFET structure without DSC and DSE implants.
Fig. 4-1 (c) The SUPREM-IV.GS simulated cross sections of the NPN GC-LBJT with three types implant profile engineering: Type III of the structure by using symmetric DSE, and lower PW implants.


Fig. 4-1 (d) The layout top view example of NPN GC-LBJT by 1x1 arrays.
Fig. 4-2 The current gain β (under VGE = – 0.3V and VCB = 0 V)of the NPN GC-LBJT with emitter area of 1 μm2 as a function of collector current with gate length as parameter for type I, II ,and III structures.
Fig. 4-3.The Gummel plot and current gain (insert) for the type I NPN GC-LBJT with gate length of 0.25μm, and emitter area of 1 μm2 as a function of VGE with variations of –0.12 V to –0.3 V (VC=0V, VB=0V). 
Fig. 4-4 The output characteristics for the type I NPN GC-LBJT with gate length of 0.25μm, and emitter area of 1 μm2 as functions of VCE biased from 0 V to 1.2 V, and VBE biased from 0.78 V to 0.92 V (VGE=-0.3V, VE =0V). 
Fig. 4-5 Normalized collectors current and drain current flicker noise versus frequency. The 1/f flicker noise characteristic of the type I structure of the 0.25μm NPN GC-LBJT with emitter area of 1 μm2, and under bias condition of VBE=0.65V, VGE = -0.3V, VCB =0 V and the NMOSFET with gate area of 1 μm2 under bias condition of VGS=0.41V, VDS = 1.2V.
Fig. 4-6 Comparison of (a) fT and (b) fmax for the type I to type I I I structures of the 0.25μm and 0.15μm NPN GC-LBJT with emitter area of 1 μm2 ,and under condition of VGE = –0.3V, and VCB =0 V, as a function of collector current.
Fig. 5-1 (a) cross section scheme for a unit cell of the GC- LV-BJTA.
Fig. 5-1 (b) novel layout for a unit cell of the GC- LV-BJTA.
Fig. 5-1 (c) conventional layout for a unit cell of the GC- LV-BJTA.
Fig. 5-1 (d) the SUPREM-IV GS simulated scheme with DSE (dedicated-sub-emitter), and dedicated-sub-collector (DSC) for a unit cell of the GC- LV-BJTA.
Fig. 5-2 Comparison of current gain for the GC- LV-BJTA with and without a deep n-well under VG =-0.25V, and emitter P/A ratio= 13.12. The insert shows the current gain of a same structure device, but with the conventional layout.
Fig. 5-3 (a) Schemes to derive the lateral collector currents of a unit cell for the GC- LV-BJTA.
Fig. 5-3 (b) Schemes to derive the vertical collector currents of a unit cell for the GC- LV-BJTA.
Fig. 5-4 The forward Gummel plot for the GC- LV-BJTA consisting 16 units with gate length of 0.16μm and emitter P/A= 13.12 as a function of gate bias VG. The measurement conditions are VC=1V, VE =0V, and P-sub= 0V.
Fig. 5-5 The current gain of the GC-LV-NPN BJTA calculated from Fig.3 as a function of collector current with the gate bias VG as parameter.
Fig. 5-6 The effect of emitter P/A ratio on collector current and base current in linear region (VBE=0.6 V) and saturation region (VBE=1.0 V) for the GC- LV-BJTA consisting 16 unit cells with gate length of 0.16μm and VG =-0.25V. The measurement conditions are VC=1V, VE =0V, and P-sub= 0V.
Fig. 5-7 The current gain of the GC-LV-NPN BJTA as a function of collector current with the emitter P/A ratio as parameter.
Fig. 5-8 (a) The 1/f flicker noise characteristics of the GC- LV-BJTA consists 16 units with gate length of 0.16μm and 0.2μm, and gate bias VG=-0.25V. The total emitter area and base drive current density of the GC- LV-BJTA are 1.5 μm2 and Jb=1 or 3μA/μm2, respectively. The 1/f noise of the NMOSFET and the SiGe NPN HBT under measurement bias conditions of VGS = 0.63V, VDS = 1.2V, and the currents of 2.5μA/μm2 and 5μA/μm2, respectively are also presented for comparison. 
Fig. 5-8 (b) Comparison of the 1/f flicker noise normalized to IC2 and ID2 for the GC- LV-BJTA SiGe NPN HBT and NMOSFET, respectively.


                                    

[1] A.M. Niknejad, R.G. Meyer, “Analysis, Design, and Optimization of Spiral Inductors and Transformers for Si RF IC’s,” IEEE J. Solid-State Circuit 33 (1998) 1470-1481.
[2] N. Zamdmer, A. Ray, J.-O. Plouchart, L. Wagner, N. Fong, K.A. Jenkins, W. Jin, P. Smeys, I. Yang, G. Shahidi, F. Assaderaghi, “A 0.13-µm SOI CMOS Technology for Low-Power Digital and RF Applications, Proc. Symp. VLSI Technology,” Dig. Tech. Papers (2001) 85-86.
[3] A. Joseph, D. Coolbaugh, M. Zierak, R. Wuthrich, P. Geiss, Z. He, X. Liu, B. Orner, J. Johnson, G. Freeman, D. Ahlgren, B. Jagannathan, L. Lanzerotti, V. Ramachandran, J. Malinowski, H. Chen, J. Chu, P. Gray, R. Johnson, J. Dunn, S. Subbanna, K. Schonenberg, D. Harame, R. Groves, K. Watson, D. Jadus, M. Meghelli, A. Rylyakov, “A 0.18 µm BiCMOS Technology Featuring 120/100 GHz (fT/fMAX) HBT and ASIC-Compatible CMOS Using Copper Interconnect,” Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (2001) 143-146.
[4] T.O. Dickson, M.-A. LaCroix, S. Boret, D. Gloria, R. Beerkens, S.P. Voinigescu, “Si-based inductors and transformers for 30-100 GHz applications,” Proc. IEEE Microwave Theory and Techniques Society Dig. (2004) 205-208.
[5] H. Darabi, A.A. Abidi, “A 4.5-mW 900-MHz CMOS receiver for wireless paging,” IEEE J. Solid-State Circuit 35 (2000) 1085-1096.
[6] C.S. Lin, Y.K. Fang, S.F. Chen, C.Y. Lin, T.H. Chou, S.M. Chen, M.C. Hsieh, “A Novel Ni Capped High Q Copper Air Gap Spiral Inductor, “ Materials Science in Semiconductor Processing 8 (2005) 545-549.
[7] C.S. Lin, Y.K. Fang, S.F. Chen, C.Y. Lin, M.C. Hsieh, C.M. Lai, T.H. Chou, C.H. Chen, “A deep submicrometer CMOS process compatible high-Q air-gap solenoid inductor with laterally laid structure,” IEEE Electron Device Lett. 26 (2005) 160-162.
[8] K.B. Ashby, I.A. Koullias, W.C. Finley, J.J. Bastek, S. Moinian, “High Q inductors for wireless applications in a complementary silicon bipolar process,” IEEE J. Solid-State Circuit 31 (1996) 4-9.
[9] M. Park, S. Lee, C.S. Kim, H.K. Yu, K.S. Nam, “The detailed analysis of high Q CMOS-compatible microwave spiral inductors in silicon technology,” IEEE Trans. Electron Devices 45 (1998) 1953-1959.
[10] Dieter K. Schroder, Semiconductor Material and Device Characterization, John Wiley & Sons, Inc. 1990.
[11] M. Shur, Physics of Semiconductor Devices. Englewood Cliffs, NJ: Prentice-Hall, 1990.
[12] B. L. Sharma, Metal-Semiconductor Schottky Barrier Junctions and Their Applications. New York: Plenum, 1984.
[13] S.Biber, O.Cojocari, G.Rehm, B.Mottet,M.Rodriguez-Girones, L.P Schmidt, H.L.Hartngel, IEEE trans. Instrum Meas. 53(2004) 581.
[14] S. Biber, O. Cojocari, G. Rehm, B. Mottet, M. R. Girones, L. P. Schmidt, H. L. Hartnagel, IEEE Transactions on Instrum. and Meas., 5 (2004) 581.
[15] J.H. Han, W. Jeon and J. Melngailis, IEEE SENSORS 2006, EXCO, Daegu, Korea / October 22-25, (2006) 1493
[16] X. N. Wang, B. Zhu, J. K. Su, T. H. Lee, L. W. Yang, 7th Int. Conf. on ASIC, Guilin, China,( 2007 ) 1138.
[17] S. A. Maas, Microwave Mixers. Boston, MA: Artech House, 1986.
[18] S. Mollenkopf and G. M. Rebeiz, IEEE MTT-S Int. Microw. Symp. San Diego, CA, USA,Dig., 3 (1994) 1347.
[19] N. Yutani, H. Yagi, M. Kimata, J. Nakanishi, S. Nagayoshi, and N. Tubouchi, Inst. Elect. Eng. Coll. Microwave and Millimeter MIC, (1991) 175.
[20] K. M. Strohm, J. Buechler, E. Kasper, J. F. Luy, and P. Russler, Inst. Elect. Eng. Coll. Microwave and Millimeter MIC, (1998) 1.
[21] K. M. Strohm, J. Buechler and E. Kasper, IEEE Trans. Microwave Theory and Tech., 46(1998) 669.
[22] S. Swaminathan and K. O. Kenneth, IEEE Electron Device Lett, 26 (2005) 492.
[23] Hashimoto T, Nonaka Y, Tominari T, Fujiwara H, Tokunaga K, Arai M, Wada S, Udo T, Seta M, Miura M, Shimamoto H, Washio K, Tomioka H. “Direction to improve SiGe BiCMOS technology featuring 200-GHz SiGe HBT and 80-nm GAT CMOS. IEDM Tech,” Dig. 2003: 5.5.1-5.5.4.
[24] Freeman G, Jagannathan B, Jeng SJ, Rieh JS, Stricker AD, Ahlgren DC, Subbanna S. “Transistor design and application considerations for > 200-GHz SiGe HBTs,” IEEE Trans. Electron Devices 2003; 50: 645-655.
[25] Washio K. “SiGe HBT and BiCMOS technologies for optical transmission and wireless communication systems,” IEEE Trans. Electron Devices 2003; 50: 656-68.
[26] Yan Z, Deen MJ, Malhi DS. “Gate-controlled Lateral PNP BJT: Characteristics, modeling and circuit applications,” IEEE Trans. Electron Devices 1997; 44: 118-28.
[27] Sankaran Aniruddhan, Min Chu, and David J. Allstot. “A Lateral-BJT-Biased CMOS Voltage-Controlled Oscillator,” IEEE ISCAS 2004; I: 976-979.
[28] Joardar K. “An Improved Analytical Model for Collector Currents in Lateral Bipolar Transistors,” IEEE Transactions on Electron Devices 1994; 41: 373-82.
[29] Sze S M. Physics of semiconductor devices. New York: John Willy &Sons; 1981.
[30] H. Nii, et.al., “A novel lateral bipolar transistor with 67 GHz fmax on thin-film SOI for RF analog applications,” IEEE Transactions on Electron Devices 2000; 47: 1536-1541.
[31] T. Suligoj, et al., “A new HCBT with a partially etched collector,” IEEE Electron Device Letters 2005; 26: 200-202.
[32] I-Shan Michael Sun, et al., “Lateral high-speed bipolar transistors on SOI for RF SoC applications,” IEEE Transactions on Electron Devices 2005; 52: 1376-1383.
[33] Zhiming Feng, Shuo-Mao Chen, CP Chao, HC Tseng, Cliff Xie, Yan Cui, Mike Brunsman, Guofu Niu, and G. Ali Rezvani. “Gate Controlled Vertical-Lateral NPN Bipolar Transistor in 90nm RF CMOS Process,” IEEE CICC 2001; 385-388.
[34] J. A. Babcock, D. K. Schroder, W. L. M. Huang and J. M. Ford, “Low-Frequency Noise in TFSOI Lateral N-P-N Bipolar Transistors,” IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 956-965, May 2001.
[35] R. P. Jindal, “Low-frequency fluctuations device, technology, and system implications,” in Quantum 1/f Noise and Other Low Frequency Fluctuations in Electronic Devices, New York, NY, 1992, pp. 1-7.
[36] D. F. Bowers, “Minimzing noise in analog bipolar circuit design,” in Proc. Bipolar and BiCMOS Circuits and Technol. Meet., Minneapolis, MN, 1989, pp. 107-111.
[37] B. Razavi, “Challenges in portable RF transceiver design,” IEEE Circuits Syst. Mag., vol. 12, no. 5, pp. 12-25, Sept. 1996.
[38] J. A. Babcock, B. Loftin, P. Madhani, X. Chen, A. Pinto and D. K. Schroder, “Comparative Low Frequency Noise Analysis of Bipolar and MOS Transistors Using an Advanced Complementary BiCMOS Technology,” in Proc. CICC, 2001, pp. 385-388.
[39] Z. X. Yan, M. J. Deen and D. S. Malhi, “Gate-controlled lateral PNP BJT: Characteristics, modeling and circuit applications,” IEEE Trans. Electron Devices, vol. 44, pp. 118-128, Jan. 1997.
[40] K. Joardar, “An Improved Analytical Model for Collector Current in Lateral Bipolar Transistor,” IEEE Trans. Electron Devices, vol. 41, pp. 373-382, Mar. 1994.
[41] S. Aniruddhan, M. Chu and D. J. Allstot, “A Lateral-BJT-Biased CMOS Voltage-Controlled Oscillator,” in Proc. IEEE ISCAS, 2004, pp. 976-979.
[42] S. Verdonckt-Vandebroek, S. S. Wong and P. K. Ko, “High Gain Lateral Bipolar Transistor,” in Proc. IEDM Tech. Dig., 1988, pp. 406-409.
[43] J. Olsson, B. Edholm, A. Soderbarg and K. Bohlin, “High Current Gain Hybrid Lateral Bopolar Operation of DMOS Transistors,” IEEE Trans. Electron Devices, vol. 42, pp. 1628-1635, Sept. 1995.
[44] T. Hashimoto, Y. Nonaka, T. Tominari, H. Fujiwara, K. Tokunaga, M. Arai, S. Wada, T. Udo, M. Seta, M. Miura, H. Shimamoto, K. Washio and H. Tomioka, “Direction to improve SiGe BiCMOS technology featuring 200-GHz SiGe HBT and 80-nm GAT CMOS,” in Proc. IEDM Tech. Dig., 2003, pp.129-132.
[45] G. Freeman, B. Jagannathan, S. J. Jeng, J. S. Rieh, A. D. Stricker, D. C. Ahlgren and S. Subbanna, “Transistor design and application considerations for > 200-GHz SiGe HBTs,” IEEE Trans. Electron Devices, vol. 50, pp. 645-655, Mar. 2003.
[46] K. Washio, “SiGe HBT and BiCMOS technologies for optical transmission and wireless communication systems,” in Proc. IEDM Tech. Dig., 2003, pp. 113-116.
[47] H. Nii, T. Yamada, K. Inoh, T. Shino, S. Kawanaka, M. Yoshimi and Y. Katsumata, “A novel lateral bipolar transistor with 67 GHz f(max) on thin-film SOI for RF analog applications,” IEEE Trans. Electron Devices, vol. 47, pp. 1536-1541, Jul. 2000.
[48] T. Suligoj, P. Biljanovic, J. K. O. Sin and K. L. Wang, “A new HCBT with a partially etched collector,” IEEE Electron Device Lett., vol. 26, pp. 200-202, Mar. 2005.
[49] I. S. M. Sun, W. T. Ng, K. Kanekiyo, T. Kobayashi, H. Mochizuki, M. Toita, H. Imai, A. Ishikawa, S. Tamura and K. Takasuka, “Lateral high-speed bipolar transistors on SOI for RF SoC applications,” IEEE Trans. Electron Devices, vol. 52, pp. 1376-1383, Jul. 2005.
[50] N. Shiono, “Emitter perimeter-to-area ratio effects on high frequency transistor current gain and its degradation,” Jpn. J. Appl. Phys., vol.18, pp. 1097-1102, 1979.
[51] J.Lindmayer and C. Y. Wrigley, “Beta Cutoff Frequencies of Junction Transistors,” in Proc. IRE, 1962, pp. 194-198.
[52] H. K.Gummel, “On the definition of the cutoff frequency fT,” in Proc. IEEE, 1969, pp. 2159-2159.

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