隨著積體電路線寬不斷縮小，晶圓表面高低起伏對微影聚焦能力影響很大，使得晶圓平坦化的要求不斷提升。化學機械研磨於半導體元件製程技術中已被公認為最有效之全面性平坦化技術，而其研磨均勻度對晶圓元件之良率有重大之影響。微觀製程所遭遇到的問題，即在CMP製程中當研磨墊研磨至SiO2介電層與銅導線時，因為兩者之間材料性質有所差異，如硬度不同，抗磨性也不同，因此在相同負載條件下，會造成銅材料的移除率較高，使得導線銅部分形成淺碟型的凹陷及應力腐蝕型缺陷，形成缺陷。過去許多人以理論分析、有限元素法或實驗經驗法則針對化學機械研磨提出許多預測研磨率或缺陷之模型。以純有限元素法或以接觸力學理論分析進行之CMP模擬因無法模擬研磨過程之形貌改變，僅能利用初始幾何做為模擬依據，因而可能產生誤差。有鑑於此，本文提出一新型製程模擬方式，作為改善CMP模擬的方向。本文利用有限元素分析結合MATLAB建立一套製程模擬工具。先以FEM建立一CMP模型，根據模型之幾何與受力狀態，由有限元素法可得此時晶圓之應力狀態，再由MATLAB作控制及計算，計算完成後更新CMP模型進行下一次研磨，依此可簡單的控制研磨次數及研磨參數(如晶圓與研磨墊之材料常數、研磨墊與晶圓相對速度、Preston’s coefficient等)，從而探討研磨參數與晶圓表面形貌之關係，可依據各種情形調整所需要的參數。而模擬結果與過去研究之實驗與模擬相互比較以驗證此方法之可行性。其結果將更可提供CMP製程最佳化參考。

Chemical mechanical polishing (CMP) has been recognized as the most effective planarization technology in wafer processing, and its plays an important role in the state of the arts integrated circuits (IC) fabrication. For CMP, the polishing uniformity of entire wafer as well as the possible dishing and erosion observed in interconnects are the most critical concerns and therefore various analytical and numerical investigations have been conducted for enhancing CMP performance. However, due to its multi-disciplinary nature, it is difficult to conduct a full scale analysis. In particular, finite element analysis (FEA) has been widely used in associated with polishing model such as Preston’s equation for predicting the mechanical stressing effect in CMP. However, in the past, due to lack of efficient geometry updating capability, FEA can only use the initial geometry for simulation, which cannot count the geometry evolution and could possibly results in error. For this reason, in this thesis, a novel chemical-mechanical polishing modeling schemes for addressing the mechanical aspect in both wafer and device levels is analyzed and realized. The method integrates finite element analysis with Matlab for controlling the simulation geometry. The method begins with a CMP finite element model and, the stress of a particular step can be determined and the corresponding MRR can be calculated by FEA. Consequently, the surface topology is then updated based on the calculated MRR distribution, using Matlab and is used for FEA at next time increment. The interaction continues until the entire process is finished. Both wafer and device level simulations are performed by the proposed method. In wafer level, it is observed that the discrepancy between the proposed method and the traditional FEA based on initial geometry is not significant for high uniformity variation tolerance. However, as the tolerance reduceds to within 10 nm, the difference in uniformity prediction becomes remarkable. On the other hand, for device level, the proposed method can successfully predict dishing and erosion phenomena and the simulation results agree with those experimental data reported in previous literatures. Finally, essential parametric studies are performed for systematically investigating various processing parameters such as pad modulus and selectivity as demonstrations for addressing the structural integrity of interconnected structures after polishing and for the possible applicability of using the proposed method for guiding future CMP process optimization.

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