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研究生: 莊博凱
Chuang, Po-Kai
論文名稱: 使用步階式阻抗之小型化與低插入損失CMOS毫米波單頻與雙頻帶通濾波器
Research on Compact and Low-Insertion-Loss CMOS Millimeter-Wave Single- and Dual-Band Bandpass Filters Using Stepped-Impedance Resonators
指導教授: 莊惠如
Chuang, Huey-Ru
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年: 2015
畢業學年度: 103
語文別: 中文
論文頁數: 77
中文關鍵詞: 毫米波小型化低插入損失步階式阻抗帶通濾波器
外文關鍵詞: RF bandpass filter (BPF), CMOS, compact, dual-band, low-insertion-loss, millimeter-wave (MMW), stepped-impedance (SI)
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  • 本論文研製使用步階式阻抗之小型化、低插入損失CMOS毫米波60-GHz、77-GHz與60-/110-GHz、24-/77-GHz雙頻帶通濾波器,分別採用TSMC CMOS 0.18-μm與90-nm GUTM製程。60-GHz 步階式阻抗負載平行耦合線帶通濾波器,選用短路平行耦合線搭配兩段式步階阻抗開路截線作為負載以達到微小化。77-GHz反向平行耦合線帶通濾波器具有兩個可調式傳輸零點,使用兩段式步階阻抗開路耦合線及並聯兩段式步階阻抗開路截線之架構,可方便調控兩側傳輸零點位置,具有陡峭的選擇性。60-/110-GHz低插入損失之步階式阻抗雙頻帶通濾波器,共振器架構為並聯三段式步階阻抗截線,導納轉換器為三段式步階阻抗傳輸線等效而成。24-/77-GHz雙頻帶通濾波器使用π型阻抗/導納轉換器架構,共振器為串聯兩段式步階阻抗傳輸線。電路設計以Agilent ADS與Ansoft 3-D全波電磁模擬軟體HFSS以及Zeland-IE3D進行模擬,量測部分則是採用on-wafer方式進行,模擬與量測皆具有良好的一致性。

    This thesis presents the research on compact and low-insertion-loss CMOS millimeter-wave (MMW) single-band (60 and 77 GHz ) and dual-band (60/110 and 24/77 GHz) bandpass filters (BPFs) using stepped-impedance (SI) resonators, implemented by standard TSMC 0.18-μm or 90-nm GUTM CMOS process. The 60-GHz BPF, consists of the short-ended coupled line and two-section SI open-circuited stub, achieves a significant size reduction. The 77-GHz BPF with the two-section SI open-ended coupled line and two-section SI open-circuited stubs has two transmission zeros for sharp band edges. For dual-band BPFs, the 60-/110-GHz BPF which consists of resonators, tri-section SI stubs, and admittance inverters provides enough design parameters to synthesize the dual-band BPF. In 24-/77-GHz BPF design, the resonators are two-section SI transmission lines, and the π-type structures are used to realize the K/J inverters. The designed MMW CMOS filters are all performed by using the on-wafer measurement. Simulation and measurement results are compared and discussed.

    第一章 緒論 1 1.1 研究背景與動機 1 1.2 射頻帶通濾波器之Figure of Merit (FOM)介紹 2 1.3 文獻探討 4 1.4 論文架構 5 第二章 微小化之60-GHz CMOS步階式阻抗負載平行耦合線帶通濾波器 6 2.1 阻抗轉換器與導納轉換器合成濾波器理論 6 2.1.1 合成理論介紹[18][19] 6 2.1.2 輸入/輸出端轉換器簡化架構 8 2.2 微小化之60-GHz CMOS步階式阻抗負載平行耦合線帶通濾波器 10 2.2.1 微小化與傳輸零點設計 10 2.2.2 並聯短路與兩段式步階阻抗開路截線之n階電路架構 14 2.2.3 短路端平行耦合線與導納轉換器之等效架構 19 2.2.4 設計流程 26 2.2.5 實現二階短路端平行耦合線之帶通濾波器 27 2.2.6 模擬與量測結果 28 2.2.7 結果與討論 31 第三章 具有兩個可調式傳輸零點之77-GHz CMOS反向平行耦合線 帶通濾波器 32 3.1 傳輸零點設計 32 3.2 串聯與並聯兩段式步階阻抗開路截線之二階電路架構 34 3.3 開路端步階阻抗反向平行耦合線與阻抗轉換器之等效架構 35 3.4 設計流程 39 3.5 實現二階開路端步階阻抗反向平行耦合線之帶通濾波器 39 3.6 模擬與量測結果 40 3.7 結果與討論 44 第四章 60-/110-GHz低插入損失之CMOS步階式阻抗雙頻帶通濾波器 45 4.1 並聯三段式步階阻抗短路與開路截線之二階雙頻電路架構 45 4.2 三段式步階阻抗傳輸線與導納轉換器之等效架構 48 4.3 設計流程 51 4.4 實現二階並聯三段式步階阻抗短路與開路截線之雙頻帶通濾波器 51 4.5 模擬與量測結果 52 4.6 結果與討論 55 第五章 24-/77-GHz CMOS使用π型阻抗/導納轉換器之雙頻帶通濾波器 56 5.1 兩段式步階阻抗雙頻帶通濾波器之二階電路架構 56 5.2 π型短路截線與阻抗/導納轉換器之等效架構 59 5.3 設計流程 66 5.4 實現二階π型短路截線之雙頻帶通濾波器 67 5.5 模擬與量測結果 67 5.6 結果與討論 70 第六章 結論 71 參考文獻 73 附錄A 互補式金氧半導體(complementary metal-oxide semiconducter, CMOS)製程簡介 75

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