隨著電子元件科技技術的發展，以及奈米元件尺寸越縮越小，傳統的金氧半場效應電晶體本身以及結構上有許多問題。為了要避免和克服這些挑戰，像是隨機摻雜濃度導致的行為變化、高溫度預算效應以及載子遷移率降低等等，有許多新的元件結構和操作概念都被提出來，其中一個就是無摻雜場效應電晶體。在無摻雜場效應電晶體裡面，載子式摻雜取代傳統的化學式(雜質)摻雜來克服傳統化學式摻雜的限制，且把隨機摻雜濃度導致的行為變化降到最低。這個特色讓無摻雜場效應電晶體成為有前途的未來電晶體科技以及先進元件製造候選者。
在本論文中，我們討論傳統化學式摻雜的限制以及介紹離子電漿的概念，接著我們利用兩個不同種類的接觸:金屬-半導體及金屬-絕緣層-半導體，來討論這些接觸的電阻限制。接著我們更進一步詳細的討論幾個蕭特基(Schottky)能障理論且討論在異質接面中的費米能階釘札效應的推論與成因。這份研究主要仰賴於Sentaurus TCAD 來模擬與比較金屬-半導體與金屬-絕緣層-半導體無摻雜場效應電晶體。使用金屬-絕緣層-半導體而非金屬-半導體接面，無摻雜場效應電晶體可以在源/汲極有效減少金屬所導致的能隙能階。金屬-絕緣層-半導體無摻雜場效應電晶體更被討論能夠完全消滅無接面電晶體嚴重的隨機摻雜濃度導致的行為變化效應。我們也模擬出使用金屬-絕緣層-半導體接觸的無張力矽鍺無摻雜鰭式場效應電晶體以及奈米線場效應電晶體，且詳細地討論他們的電特性。基於這些我們所提出使用金屬-絕緣層-半導體接觸之無摻雜場效應電晶體、無接面場效應電晶體式場效應電晶體以及奈米線場效應電晶體，這些結果闡述了在先進奈米元件微縮下絕佳的潛力。

As we develop electronic devices technology and reduce the devices dimensions, there have been several problems for the operation of the traditional MOSFETs and device manufacture. In order to prevent and avoid the challenges, such as random dopant fluctuation (RDF), thermal budget and mobility degradation…etc, several new device structures and operation concepts have been proposed, and one of them is the dopingless transistors. Traditional chemical (impurity) doping is replaced by electrostatic doping in dopingless devices in order to overcome the limitation of traditional chemical doping technique and to minimize RDF. The feature makes the dopingless transistor a promising candidate for future CMOS technologies and advanced device fabrication.
In this thesis, we discuss the limitation of chemical doping and introduce the concept of charge plasma mechanism, then we utilize two different contacts and discuss the resistivity limitation of the contacts: metal-semiconductor (MS) and metal-insulator semiconductor (MIS) contacts. Next we further discuss several Schottky barrier models in detail and analyze the reason and effect of fermi-level pinning (FLP) at a heterojunction. This research relies on Sentaurus technology computer-aided design (TCAD) to simulate and compare dopingless transistors with MS and MIS contacts. Using the MIS instead of MS contacts, dopingless transistors can mitigate the fermi-level pinning effect at source/drain (S/D). Dopingless FETs with MIS contacts are also discussed to extinguish the considerable impacts of RDF in traditional doped junctionless FETs. We also simulate dopingless relaxed SiGe FinFETs and nanowire FETs with MIS contacts and analyze the electrical performances. Base on the simulation results of the novel dopingless transistors, JLFETs, FinFETs, and nanowire transistors with MIS contacts, they demonstrate superior potential for advanced nanoscale devices.

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[7] S. Gupta et al., “Contact Resistivity Reduction Through Interfacial Layer Doping in Metal-Interfacial Layer-Semiconductor Contacts,” Appl. Phys. Lett., vol. 113, no. 23, p. 234505, 2013.
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References in Appendix I
[1] J. Robertson, “Band Offsets, Schottky Barrier Heights, and Their Effects on Electronic Devices,” J. Vac. Sci. Technol. A 31, 050821, August 2013.

References in Appendix II
[1] J. F. Wager et al., “Device Physics Modeling of Surfaces and Interfaces from an Induced Gap State Perspective,” Critical Reviews in Solid State and Materials Sciences, Vol. 0, No. 0, pp.1-43, 2016.

References in Appendix V
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