在現今的晶片後端設計過程中，電路設計師需要耗費大量時間進行電路布局繞線及合成。更不用提及修正到達成目標所花費時間。本篇研究試圖透過神經網路模型學習現今商業軟體對於設計電路的公式，再訓練生成對抗模型試圖讓參數選擇可以達到最佳化，由於這些商業軟體內含大量具經驗的規則，可以透過神經網路試著學習規則，本篇內容主要著重在最佳化電路設計中合成時鐘樹的過程。
在本篇論文中，試圖對先前有利用深度學習應用於輔助時鐘樹的論文加以改善，我們成功讓合成時鐘樹的結果優於先前作者的單一生成模型。在設計的四個模型中，從特徵抽取、時鐘樹合成結果的預測到最後對未見過電路推薦一組CTS (Clock Tree Synthesis)參數，試圖讓電路時鐘樹合成能夠最佳化。
使用回歸模型預測時鐘樹的結果，對測試資料計算的誤差可以來到MAPE (Mean Absolute Percentage Error) 13%的誤差。當應用回歸模型於CTS-GAN生成模型時，效果也相當顯著，對不同類型測試電路，各項指標相較於商業軟體的預設，skew(時鐘偏差)最多可以減少33%，clock wire (時鐘樹線長)減少1.4%，clock power 則是21%。
本篇論文加以考慮時鐘偏移(clock skew)，時鐘功耗(clock power)，時鐘線長(clock wire)三者關係，發現時鐘偏移與另外兩者關係不高甚至在某些電路呈現負相關，於是在生成模型中加入優先權選擇後，skew(時鐘偏差)可以減少29%，clock wire (時鐘樹線長)減少5%，clock power (時鐘功耗)則是22%，最終結果在測試電路中也能將各項指標降得更低。

In the current chip back-end design process, circuit designers need to spend a significant amount of time on layout, routing, and synthesis. This study aims to use neural network models to learn the rules used by modern commercial software for circuit design and train a generative adversarial model to optimize parameter selection. Since these commercial software packages contain a vast number of experienced rules, neural networks can be used to learn these rules. Therefore, this study focuses on optimizing the clock tree synthesis process in circuit design.
This study attempts to improve previous studies that have applied deep learning to assist in clock tree synthesis. We have successfully achieved better clock tree synthesis results compared to the single generative model used by previous researchers. We designed four models, covering feature extraction, prediction of clock tree synthesis results, and finally recommending a set of CTS (Clock Tree Synthesis) parameters for unseen circuits to optimize clock tree synthesis.
This paper considers the relationships among clock skew, clock power, and clock wire length, and finds that clock skew has a low correlation with the other two, even showing a negative correlation in some circuits. By incorporating priority selection into the generation model, clock skew can be reduced by 29%, clock wire length by 5%, and clock power by 22%. The final results also demonstrate that these metrics can be further reduced in the test circuits.

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