車輛在今日已是最不可或缺交通工具之一，而有關車輛的識別，也成為重要的應用方向，因此車牌辨識(License Plate Recognition)的相關方法紛紛被提出和實際運用。車牌辨識包含數個步驟，首先透過邊緣偵測和形態學等影像處理方式，將車牌區域定位出來並切割，接著進行垂直投影與水平投影判斷出字元集中之處，以將車牌非字元區域去掉，之後進行二值化處理和字元切割，最後透過樣板比對(Template Matching)方式來辨識字元內容。
在此論文中，我們即提出一基於上述各方式之VLSI架構，以期提高整體運作速度。我們使用SYNOPSYS Design Vision和TSMC 0.13µm的標準元件庫來合成電路，合成結果顯示該電路的邏輯閘數目為55585，工作於12ns時脈之頻率為83MHz。模擬結果顯示在本文所提出硬體電路架構下，車牌辨識所需時間從40ms~60ms加快至6ms~7ms。

Vehicle is the most indispensable transport today, and the vehicle recognition also becomes an important application direction. So related methods for license plate recognition have been proposed and used. License plate recognition includes several steps: first it executes the edge detection and morphological image processing methods, then cuts and locates the license plate region. It determines the character region and removes non-character region by the vertical projection and horizontal projection, and then executes the binary processing and characters cutting. Finally it uses template matching approach to identify character content.
In this paper, we purpose the VLSI architectures about the above methods to improve the whole speed. We used SYNOPSYS Design Vision to synthesize the circuits with TSMC 0.13µm cell library. Synthesis results show that the circuits contain 55607 gates. It work with a clock period of 12 ns and achieve a processing rate of 83MHz. Simulation results show that license plate recognition time improved from 40ms ~ 60ms to 6ms ~ 7ms in the proposed hardware circuit architecture of this paper.

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