隨著半導體科技快速發展，半導體元件大小須持續下降，進而使積體電路操作速度與效能持續提升。但是當半導體元件持續縮小的同時，薄膜沉積時產生的微小缺陷也就成為影響積體電路操作速度與效能的隱形殺手。
現今，許多的介電層使用電漿輔助式化學氣相沉積的方法生成，部分沉積過程使用有機分子的先驅物作為反應氣體。當沉積介電層到達需求的厚度時，反應氣體將被關閉並停止沉積。然而腔體內的殘留氣體將繼續和薄膜表面反應進而產生缺陷。產生缺陷的原因來自於使用電漿沉積後，薄膜表面生成的懸浮鍵，可能會和殘留離子群結合，在薄膜表面形成大小小於0.05微米的缺陷。然而此種微小缺陷可能嚴重影響下游製程以及產品穩定度。
此篇論文探討有關半導體製程中，沉積薄膜時微小缺陷產生的機制及研究減少微小缺陷產生的方法。

To further improve the chip speed or the performance of the integrated circuits (ICs), continuous shrinkage of the IC feature size is inevitable. However, in order to have a great yield on products, the nanometer size defects deposited on a dielectric film no longer can be ignored.
In the IC fabrication, several dielectric layers are formed by plasma enhanced chemical vapor disposition (PECVD) technique, which uses precursors containing organic molecules as reactant gases. In the PECVD process, a pre-determined thickness of a dielectric layer is formed on a substrate, the sources of the reactant gases have to be turned off to stop the deposition. The remaining reactant gases, however, could continue to dissociate and to react after the power turn off. Dangling bounds formed on the film surface may capture the residual radicals or the remaining ionic groups which dissociated from the precursors, and they are prone to congregate and form in clusters on the surface of the film. Their presence on the film surface acting as particles, or as defects, and are smaller than 0.05μm. As a result, such defects may seriously impact the subsequent processes, product yield and reliability.
The present thesis investigates how the defects are created and develops a method to minimize the defect creation in the dielectric film.

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