| 研究生: |
徐曉秋 Hsu, Hsiao-chiu |
|---|---|
| 論文名稱: |
新型奈米線薄膜電晶體之製備與探討 The fabrication and study of novel nanowire thin-film transistor |
| 指導教授: |
洪昭南
Hong, Chau-Nan Franklin |
| 學位類別: |
碩士 Master |
| 系所名稱: |
工學院 - 化學工程學系 Department of Chemical Engineering |
| 論文出版年: | 2005 |
| 畢業學年度: | 93 |
| 語文別: | 中文 |
| 論文頁數: | 143 |
| 中文關鍵詞: | 薄膜電晶體 、奈米線 |
| 外文關鍵詞: | Thin-film transistor, Nanowire |
| 相關次數: | 點閱:62 下載:3 |
| 分享至: |
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本論文主要分為三大部分,分別是利用介電泳力排列奈米線、製備奈米線薄膜電晶體元件及奈米線薄膜電晶體之元件特性量測與分析。在本文中主要是利用氧化鋅(ZnO)奈米線進行介電泳力實驗及製備奈米線薄膜電晶體。
在介電泳力排列奈米線的實驗方面,將探討不同外加電場強度、外加電場頻率及改變奈米線懸浮液濃度,對奈米線排列的影響,其中當外加電場大於8.8Vp-p及外加電場頻率提升至1MHz時,其奈米線較均勻排列在電極兩端。而當奈米線懸浮液濃度提升時,排列的奈米線也有增多的趨勢。
在製備氧化鋅奈米線薄膜電晶體方面,由製作的過程發現添加LOR層,可有效提升製備元件的良率。其中當將烘烤LOR層設定為200℃時,可以獲得最佳的底切(Undercut)蝕刻速率。
至於在奈米線薄膜電晶體元件的量測方面,將探討使用不同成長方式的奈米線、不同的元件結構及製備流程中後段熱處理等因素對於元件特性的影響。其中可以發現當改善元件結構時,其元件閘極電壓控制奈米線薄膜電晶體的效率也會隨之提升,提高元件的效率,其元件特性為ON/OFF 比值約為5×102,臨界電壓值約-1.2V,載子傳輸速率約2.3 cm2V-1s-1;之後,比較未熱處理的氧化鋅奈米線薄膜電晶體之元件特性,其ON/OFF 比值約為~102,臨界電壓值約在-6.5V,其載子傳輸速率~2.6 cm2V-1s-1。
Three subjects on the n-type ZnO nanowire Thin-Film transistor(n-ZnO NWs-TFT) have be studied. There are including (1)alignment of nanowire by Dielelctrophoresis, (2)fabricated NWs-TFT with LOR layer or not, and (3)analysis the characteristic of NWs-TFT under different conditions.
Using dielectrophoresis force to align nanowires has two important effects: The magnitude of E-field and the frequency of E-field. When the E-field increased to 8.8 Vp-p and the frequency increased to 1MHz, we observed the alignment of NWs getting more obvious. The number of aligned NWs are also increased following the increasing the concentration of the solution with NWs dispersed.
Added the LOR layer during the fabricated NWs-TFT process, the succeed probability is also increased. We also find the best parameter of prebaking temperature is 200℃ and get the most appropriate undercut rate of LOR layer.
There are several factors for NWs-TFT that we also demonstrated, including (1)Produced different grew method ZnO NWs into NWs-TFT,
(2)Two different structure of the NWs-TFT,
And (3)Post annealing process effect the characteristics of NWs-TFT.
When the structure changed into another one, the characteristics are also observed. Under this condition, the device’s ON/OFF ratio is ~5×102, carrier mobility is 2.3 cm2V-1s-1 and VTH is about -1.2V. Then, we compare the post-annealing effect on the same NWs-TFT device. The characteristics of NWs-TFT without post-annealing process are the ON/OFF ratio~102, carrier mobility 2.6 cm2V-1s-1 and VTH is about -6.5V.
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