簡易檢索 / 詳目顯示

回結果列表
研究生： 梁辰
Liang, Chen
論文名稱： 低溫互補式場效電晶體之次臨界擺幅飽和現象的解析建模 — 考量源汲穿隧效應與能帶尾態展寬
Analytical Modeling of Subthreshold Swing Saturation in Cryogenic CFETs Considering Source-to-Drain Tunneling and Band-Tail Broadening
指導教授： 王永和
Wang, Yeong-Her
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年： 2026
畢業學年度： 114
語文別： 英文
論文頁數： 116
中文關鍵詞： 低溫 CMOS 、互補式場效電晶體 、次臨界擺幅飽和 、源汲穿隧 、能帶尾態展寬 、解析建模 、TCAD 模擬 、量子計算
外文關鍵詞： Cryogenic CMOS, Complementary FET (CFET), Subthreshold swing saturation, Source-to-drain tunneling, Band-tail broadening, Analytical modeling, TCAD simulation, Quantum computing
相關次數： 點閱：5  下載：0 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 隨著半導體製程持續邁向 3 奈米節點以下並逐步進入量子計算時代，具備垂直整合優勢與低溫操作潛力的互補式場效電晶體（Complementary FET, CFET）已成為下一代電子元件的重要候選技術。然而，實驗已觀察到低溫下次臨界擺幅（subthreshold swing, SS）會在深低溫區發生飽和現象並偏離波茲曼熱極限，此現象對低溫 CMOS 微縮構成根本性的限制。傳統基於漂移–擴散模型的 TCAD 模擬因缺乏源汲穿隧（source-to-drain tunneling, SDT）與能帶尾態展寬（band-tail broadening）機制，無法重現此飽和行為。
    本論文提出一套適用於低溫 CFET 之 SS 飽和解析模型，將 Urbach 能帶尾態能量 E₀ 與源汲穿隧特徵能量 Wsdt 透過 quadrature sum 形式整合，建立從室溫至深低溫均適用之兩區域統一表達式，並推導出考量 CFET 上下層耦合電容 Cinter 之電靜學因子 η。本研究同時延伸 Natori-Lundstrom 彈道輸運框架，建立涵蓋次臨界區至強反轉區之完整 Id–Vg 解析模型，與 SS 模型共同構成完整的分析工具。
    所提出之 SS 模型以三組獨立資料 — Bohuslavskyi 2019（FD-SOI）、Beckers 2020（bulk Si）、Kao 2020（NEGF）中之十個資料點進行驗證，所有預測值均落於 ±20% 誤差範圍內，其中九點為零自由參數預測。將驗證後之模型應用於三層堆疊式 CFET 結構，預測 4 K 時 W = 20 nm 之 nMOS 與 pMOS 飽和 SS 分別為 15.4 mV/dec 與 13.4 mV/dec，幾乎等同於 77 K 時之波茲曼極限值（15.3 mV/dec），意即 SS 飽和現象使元件損失約 73 K 之理論優勢。此外，於 VDD = 1 V 條件下模擬 CFET 反相器之電壓傳輸特性 (VTC)，定性確認低溫時元件層級之 n/p 不對稱性直接反映於反相器切換臨界電壓的溫度依賴性偏移。本研究凸顯了釐清並抑制 SS 飽和機制對未來低溫 CFET 元件設計與量子計算電子學發展的重要性。

    As semiconductor technology scales into the sub-3-nm regime and approaches the era of quantum computing, complementary FETs (CFETs) operating at cryogenic temperatures have emerged as a leading candidate for next-generation electronics due to their compact vertical integration and low-temperature performance benefits. However, the subthreshold swing (SS) of cryogenic MOSFETs has been experimentally observed to saturate at deep-cryogenic temperatures, deviating significantly from the Boltzmann thermal limit. This phenomenon poses a fundamental constraint on cryogenic CMOS scaling, yet conventional drift-diffusion-based TCAD simulations are unable to reproduce it due to the absence of source-to-drain tunneling (SDT) and band-tail broadening in the underlying transport model.
    This thesis presents an analytical framework for cryogenic SS saturation in CFETs, in which the Urbach band-tail energy E₀ and the source-to-drain tunneling characteristic energy Wsdt are combined through a quadrature sum to yield a unified two-regime expression valid from room temperature down to deep-cryogenic temperatures, along with a CFET-specific electrostatic factor η that incorporates the inter-layer coupling Cinter. A companion ballistic Id–Vg model, built on the Natori-Lundstrom framework and extended to capture both subthreshold and strong-inversion regimes, completes the analytical toolkit.
    The proposed SS model is validated against three independent datasets — Bohuslavskyi 2019 (FD-SOI), Beckers 2020 (bulk Si), and Kao 2020 (NEGF) — covering ten data points across nearly two decades of SS values. All ten predictions fall within the ±20% accuracy band, with nine being zero-free-parameter predictions. The validated model is then applied to the simulated 3-tier CFET, predicting saturated SS values of 15.4 mV/dec for the W = 20 nm nMOS and 13.4 mV/dec for the W = 20 nm pMOS at 4 K — nearly identical to the Boltzmann limit at 77 K (15.3 mV/dec). Furthermore, CFET inverter voltage transfer characteristics (VTC) simulated at V_DD = 1 V qualitatively confirm that this device-level n/p asymmetry manifests as a temperature-dependent shift in the inverter switching threshold at cryogenic temperatures. This implies that SS saturation effectively negates 73 K of theoretical improvement, highlighting the critical importance of understanding and mitigating this phenomenon for the design of cryogenic CFET-based circuits and future quantum computing electronics.

    摘要 I Abstract III 誌謝 V Contents VII List of Figures XI List of Tables XIV Chapter 1 Introduction 15 1.1 Background 15 1.2 Motivation 20 1.3 Introduction of Synopsys Sentaurus TCAD 23 Chapter 2 A Ballistic Transport Model & TCAD Method 25 2.1 Landauer form Ballistic subthreshold current 25 2.1.1 Explain of ϕ_min 27 2.1.2 Explain of Ψ_TH 35 2.1.3 n_3D from Fermi–Dirac distribution 37 2.1.4 QTH and Φ_TH from the Constant-Current Method 38 2.1.5 Verification of n_3DUsing the Current-Density Relation 40 2.1.6 Threshold Capacitance for BTM 41 2.1.7 Mobility Driven Current for BTM 42 2.1.8 Effective minimum potential correction 42 2.1.9 Explanation of m_sub 44 2.1.10 Definition of A_pref 45 2.1.11 Definition of V_sat 45 2.1.12 Explanation of K_bal 46 2.1.13 Explanation of ΔV 47 2.2 Subthreshold Swing in Cryogenic Model 48 2.2.1 Derivation of the Electrostatic Factor η 48 2.2.2 High-Temperature Regime (T≳50K): Derivation of E_char=k_B T 52 2.2.3 Carrier Density Above the Barrier 53 2.2.4 Coupling to the Surface Potential 53 2.2.5 Diffusion-Limited Subthreshold Current 54 2.2.6 Extraction of E"char" 54 2.2.7 Cryogenic Regime (T≲50K), Part I: Derivation of the Source-to-Drain Tunneling Term W_sat 55 2.2.8 Cryogenic Regime, Part II: Derivation of the Band-Tail Term E_0 59 2.2.9 Combined Cryogenic Formula: Justification of the Quadrature Sum 62 2.3 Simulation Methodology 65 2.3.1 TCAD Environment 66 2.3.2 Structure of CFET Structure 66 2.3.3 The Physic Model in TCAD 68 2.4 Parameter Extraction and Calculation 81 2.4.1 Threshold Voltage 81 2.4.2 Subthreshold Swing 82 2.4.3 Drain-Induced Barrier Lowering (DIBL) 83 2.4.4 Ion & Ioff 84 2.4.5 Capacitance 85 2.4.6 Delay 85 2.4.7 Potential 86 Chapter 3 Results & Discussion 87 3.1 Optimization of CFET 87 3.1.1 Transfer Characteristics at Various Temperatures 88 3.1.2 Impact of Temperature on Subthreshold Swing 91 3.1.3 Impact of Temperature on DIBL and Threshold Voltage 93 3.2 Model and the Simulation Result 95 3.2.1 Validation of the Id-Vg Model 96 3.2.2 Validation of SS Model – Band-Tail Mechanism 97 3.2.3 Validation of the SS Model – Source-to-Drain Tunneling Mechanism 99 3.2.4 Aggregate Validation Across All Datasets 101 3.2.5 Extracted Model Parameters 103 3.3 Preliminary Voltage Transfer Characteristics of the CFET Inverter 104 Chapter 4 Conclusion 106 Chapter 5 Future Works 108 5.1 Quantitative Circuit-Level Analysis at Cryogenic Temperatures 108 5.2 Gate Length Dependence and SDT Mitigation 108 5.3 Self-Heating Effects in Stacked CFET at Cryogenic Temperatures 109 Chapter 6 References 110

    [1] International Roadmap for Devices and Systems (IRDS™), 2023 Edition, "More Moore," IEEE, 2023. [Online]. Available: https://irds.ieee.org/
    [2] W. Cao, H. Bu, M. Vinet, M. Cao, S. Takagi, S. Hwang, T. Ghani, and K. Banerjee, "The future transistors," Nature, vol. 620, no. 7974, pp. 501–515, Aug. 2023.
    [3] D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "FinFET—A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320–2325, Dec. 2000.
    [4] D. Jang, D. Yakimets, G. Eneman, P. Schuddinck, M. G. Bardon, P. Raghavan, A. Spessot, D. Verkest, and A. Mocuta, "Device exploration of nanosheet transistors for sub-7-nm technology node," IEEE Trans. Electron Devices, vol. 64, no. 6, pp. 2707–2713, Jun. 2017
    [5] J. Ryckaert et al., "The complementary FET (CFET) for CMOS scaling beyond N3," in Proc. IEEE Symp. VLSI Technol., 2018, pp. 141–142.
    [6] H. Mertens et al., "Nanosheet-based complementary field-effect transistors (CFETs) at 48 nm gate pitch, and middle dielectric isolation to enable CFET inner spacer formation and multi-Vt patterning," in Proc. IEEE Symp. VLSI Technol. Circuits, 2023, pp. 1–2.
    [7] H. Bohuslavskyi et al., "Cryogenic subthreshold swing saturation in FD-SOI MOSFETs described with band broadening," IEEE Electron Device Lett., vol. 40, no. 5, pp. 784–787, May 2019.
    [8] A. Beckers, F. Jazaeri, and C. Enz, "Theoretical limit of low temperature subthreshold swing in field-effect transistors," IEEE Electron Device Lett., vol. 41, no. 2, pp. 276–279, Feb. 2020.
    [9] S.-G. Jung, D. Jang, S.-J. Min, E. Park, and H.-Y. Yu, "Device design guidelines of 3-nm node complementary FET (CFET) in perspective of electrothermal characteristics," IEEE Access, vol. 10, pp. 41112–41123, 2022.
    [10] R. Landauer, "Spatial variation of currents and fields due to localized scatterers in metallic conduction," IBM J. Res. Dev., vol. 1, no. 3, pp. 223–231, Jul. 1957.
    [11] K. Natori, "Ballistic metal-oxide-semiconductor field effect transistor," J. Appl. Phys., vol. 76, no. 8, pp. 4879–4890, Oct. 1994.
    [12] M. Lundstrom, Fundamentals of Nanotransistors. Singapore: World Scientific, 2017.
    [13] R. Kim and M. Lundstrom, Notes on Fermi-Dirac Integrals, 2nd ed. West Lafayette, IN, USA: Network for Computational Nanotechnology, Purdue University, Sep. 2008
    [14] J. J. Liou, H. W. Gao, Y. H. Wang, and T. K. Chiang, "A unified quasi-3D subthreshold behavior model for multiple-gate MOSFETs," IEEE Transactions on Nanotechnology, vol. 17, no. 4, pp. 763-771, Jul. 2018
    [15] B. Sun et al., "Analytical model of CFET parasitic capacitance for advanced technology nodes," IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 936–941, Mar. 2022.
    [16] D. A. Neamen, Semiconductor Physics and Devices, 4th ed. New York, NY, USA: McGraw-Hill, 2012.
    [17] K.-H. Kao et al., "Subthreshold swing saturation of nanoscale MOSFETs due to source-to-drain tunneling at cryogenic temperatures," IEEE Electron Device Lett., vol. 41, no. 9, pp. 1296–1299, Sep. 2020.
    [18] J. Wang and M. Lundstrom, "Does source-to-drain tunneling limit the ultimate scaling of MOSFETs?," in IEDM Tech. Dig., 2002, pp. 707–710.
    [19] T. Jiao and H. Y. Wong, "Robust cryogenic ab-initio quantum transport simulation for Lg ≤ 10 nm nanowire," Solid-State Electron., vol. 197, art. no. 108440, Nov. 2022.
    [20] M. Han, P.-Y. Chiang, M. M. Radu, and C. Enz, "Physics-based and closed-form model for cryo-CMOS subthreshold swing," IEEE Trans. Nanotechnology, vol. 22, pp. 590–596, 2023.
    [21] A. Beckers, "Theoretical limit of MOSFET subthreshold swing at sub-Kelvin temperatures," IEEE Electron Device Lett., vol. 46, no. 12, pp. 2309–2312, Dec. 2025.
    [22] Synopsys, Sentaurus Device User Guide, Version R-2022.03. Mountain View, CA, USA: Synopsys, Inc., Mar. 2022.
    [23] D. B. M. Klaassen, "A unified mobility model for device simulation-II. Temperature dependence of carrier mobility and lifetime," Solid-State Electronics, vol. 35, no. 7, pp. 961-967, 1992.
    [24] D. B. M. Klaassen, "A unified mobility model for device simulation—II. Temperature dependence of carrier mobility and lifetime," Solid-State Electron., vol. 35, no. 7, pp. 961–967, Jul. 1992.
    [25] D. B. M. Klaassen, "A unified mobility model for device simulation—II. Temperature dependence of carrier mobility and lifetime," Solid-State Electron., vol. 35, no. 7, pp. 961–967, Jul. 1992.
    [26] S. Basu, B. J. Lee, and Z. M. Zhang, "Infrared radiative properties of heavily doped silicon at room temperature," J. Heat Transfer, vol. 132, no. 2, art. no. 023301, Feb. 2010, doi: 10.1115/1.4000171.
    [27] I. Isakov, H. Faber, A. D. Mottram, S. Das, M. Grell, A. Regoutz, R. Kilmurray, M. A. McLachlan, D. J. Payne, and T. D. Anthopoulos, "Quantum confinement and thickness-dependent electron transport in solution-processed In2O3 transistors," Adv. Electron. Mater., vol. 6, no. 12, art. no. 2000626, Dec. 2020.
    [28] S. Rein, Lifetime Spectroscopy: A Method of Defect Characterization in Silicon for Photovoltaic Applications, Springer Series in Materials Science, vol. 85. Berlin, Germany: Springer-Verlag, 2005.
    [29] D. K. Schroder, Semiconductor Material and Device Characterization, 2nd ed. New York, NY, USA: Wiley, 1998.
    [30] S. Harrison, "Exploring and exploiting charge-carrier confinement in semiconductor nanostructures: Heterodimensionality in sub-monolayer InAs in GaAs and photoelectrolysis using type-II heterojunctions," Ph.D. dissertation, Dept. of Physics, Lancaster Univ., Lancaster, U.K., Nov. 2016.
    [31] COMSOL AB, COMSOL Multiphysics® v. 6.4, Lombardi Surface Mobility Application Library Model, Stockholm, Sweden, 2024. [Online]. Available: https://www.comsol.co.
    [32] C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, "A physically based mobility model for numerical simulation of nonplanar devices," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 7, no. 11, pp. 1164–1171, Nov. 1988.
    [33] K. Huet, J. Saint-Martin, A. Bournel, S. Galdin-Retailleau, P. Dollfus, G. Ghibaudo, and M. Mouis, "Monte Carlo study of apparent mobility reduction in nano-MOSFETs," in Proc. European Solid-State Device Research Conf. (ESSDERC), Munich, Germany, Sep. 2007, pp. 382–385.
    [34] M. S. Shur, "Low ballistic mobility in submicron HEMTs," IEEE Electron Device Lett., vol. 23, no. 9, pp. 511–513, Sep. 2002.
    [35] R. J. Pieper and S. Michael, "An exact analysis for freeze-out and exhaustion in single impurity semiconductors," in Proc. 2005 American Society for Engineering Education (ASEE) Annual Conference & Exposition, Portland, OR, USA, Jun. 2005, pp. 10.166.1–10.166.10.
    [36] W. Shockley and W. T. Read, Jr., "Statistics of the recombinations of holes and electrons," Phys. Rev., vol. 87, no. 5, pp. 835–842, Sep. 1952.
    [37] F. Balestra and G. Ghibaudo, "Brief review of the MOS transistor physics for low temperature electronics," Solid-State Electron., vol. 37, no. 12, pp. 1967–1975, Dec. 1994.
    [38] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, 2nd ed. Cambridge, U.K.: Cambridge Univ. Press, 2009.
    [39] D. Jang, S.-G. Jung, S.-J. Min, and H.-Y. Yu, "Electrothermal characterization and optimization of monolithic 3D complementary FET (CFET)," IEEE Access, vol. 9, pp. 158116–158121, 2021.

    QR CODE