MPEG-4 為一廣為人知的多媒體編碼標準。在各種多媒體的來源之中，影像壓縮總是比其他的來源需要更多的計算量。由於資訊家電 (IA) 產品日趨普及的緣故，即時的影像編碼技術便成了一種需求。在各個計算單元之中，動態估測 (Motion Estimation, ME) 乃是改善編碼速度的最重要關鍵。在這份論文之中，我們提出了一種新動態估測的方法，它能夠降低硬體設計上的複雜度。它僅使用位元圖層進行計算；不同的搜尋方法也在此被使用和評估。效能方面和完全搜尋法 (Full Search, FS) 及三步搜尋法 (Three Step Search, TSS) 做比較，複雜度方面則是和其他的二元搜尋法做比較。
　這篇論文的第二部分提供了以ARM-9 RISC CPU為基準的編碼器硬體設計。其中完全為硬體的部分包含了動態估測(ME)、動態補償(Motion Compensation, MC)、離散餘絃轉換/反離散餘絃轉換 (Discrete Cosine Transform/Inverse Discrete Cosine Transform , DCT/IDCT)、量化器/反量化器(Quantize/Inverse Quantize, Q/IQ)、以及可變長度編碼器(Variable Length Coder, VLC)。這些功能單元都被視為ARM核心中的協同處理器 (coprocessors)。再加入一個可控制和編碼的軟體程式；它被用來連接所有的設計，以產生正確的串流 (bitstream)。這份論文提供了一個完整的設計架構。

　MPEG-4 is an emerging multimedia codec standard. Among different media sources, video compression requires more computation than others. Because information appliance (IA) products become more and more popular, real-time video codec is a necessity. Among the computational units, Motion Estimation (ME) is the most important part for improving the coding speed. In this paper, a new ME method which targets to reduce the hardware complexity is proposed. Bit-plane operations are used exclusively. Different searching strategies are used and evaluated in this thesis. The performance is compared to Full Search (FS) method and Three Step Search (TSS) method. The complexity is compared to other binary search methods.
　The second part of this thesis is to provide an hardware encoder design around an ARM-9 RISC CPU core. The completed hardware blocks include ME, Motion Compensation (MC), Discrete Cosine Transform/Inverse Discrete Cosine Transform (DCT/IDCT), Quantizer/Inverse Quantizer (Q/IQ), and Variable Length Coder (VLC). These functional blocks are treated as co-processors of the ARM core. A control/encoding software program is used to link all the design and produce the desired bitstream. This thesis provides a complete architecture design.

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